Low-temperature Thermal Annealing Research Articles

Selective area crystallization of amorphous silicon films by low-temperature rapid thermal annealing

We report the first demonstration of selective area crystallization of amorphous silicon films using low-temperature rapid thermal annealing. Crystallization temperatures as low as 500 °C were achieved with the help of a thermally evaporated ultrathin metal layer. The selective area crystallization was accomplished by using this ultrathin metal layer to define the region to be crystallized. The edge between two regions, that which has been crystallized and that which has not, is found to be very sharp.

Sub-100-nm p+-n shallow junctions fabricated by group III dual ion implantation and rapid thermal annealing

The fabrication of p+-n junctions with depth less than 100 nm using dual ion implantation of group III species (69Ga, 115In, 11B, 49BF2) in various combinations is reported. We have investigated both the single use of heavy group III (Ga and In) ions for creating shallow junctions and the dual implant approach where Ga or In was first used for preamorphization (and doping) followed by a B or BF2 implant. The optimum cases for sub-100-nm shallow junction formation among the group III combinations evaluated are Ga/B dual ion implantation followed by low-temperature (550–600 °C) rapid thermal annealing (RTA) for 15–30 s and In/B(B or BF2) dual ion implantation with higher temperature (900–1000 °C) RTA for 10 s. Junction depths of 60–100 nm and sheet resistances of 150–300 Ω/⧠ were obtained. Shallow junction diodes fabricated by this dual ion implant technology exhibit low leakage current densities of 8–30 nA/cm2 and good ideality factors of 1.01–1.05.

Crystallized Si films by low-temperature rapid thermal annealing of amorphous silicon

Low-temperature rapid thermal annealing has been used to crystallize both undoped and doped amorphous silicon (a-Si) films deposited at low temperatures. The polycrystalline films produced are completely crystallized with time temperature budgets such as 4 min at 700 °C. Unlike deposited polycrystalline Si films, the grain size in these crystallized films is not limited by film thickness. In the case of undoped a-Si films crystallized by this approach, the resulting conductivity is comparable to that achieved in undoped polycrystalline Si films produced by much higher processing temperatures. In the case of doped a-Si films, the resulting crystallized film yields a conductivity of 160 S/cm, a value which is comparable to the highest reported for doped polycrystalline and microcrystalline silicon. These doped films are found to have mobility values of ∼13 cm2/V s.

Shallow Junction Formation in As-Implanted Si by Low-Temperature Rapid Thermal Annealing

AbstractShallow junctions were formed in single-crystal Si(100) by implantation of As at energies between 2 and 17.5 keV followed by conventional furnace annealing or by rapid thermal annealing (RTA). Cross-sectional transmission electron microscopy (XTEM) showed that defect-free shallow junctions could be formed at temperatures as low as 700 °C by RTA, with about 60% dopant activation. From a comparison of short-time and long-time annealing, it is proposed that surface image forces are responsible for the efficient removal of end-of-range (EOR) dislocation loops

Electrical properties of Ga-implanted Si p/sup +/-n shallow junctions fabricated by low-temperature rapid thermal annealing

p/sup +/-n shallow-junction diodes were fabricated using on-axis Ga/sup 69/ implantation into crystalline and preamorphized Si, at energies of 25-75 keV for a dose of 1*10/sup 15//cm/sup 2/, which is in excess of the dosage (2*10/sup 14//cm/sup 2/) required to render the implanted layer amorphous. Rapid thermal annealing at 550-600 degrees C for 30 s resulted in the solid-phase epitaxial (SPE) regrowth of the implanted region accompanied by high Ga activation and shallow junction (60-130 nm) formation. Good diode electrical characteristics for the Ga implantation into crystalline Si were obtained; leakage current density of 1-1.5 nA/cm/sup 2/ and ideality factor of 1.01-1.03. Ga implantation into preamorphized Si resulted in a two to three times decrease in sheet resistance, but a leakage current density orders of magnitude higher. >

A structural and electrical comparison of thin SiO2 films grown on silicon by plasma anodization and rapid thermal processing to furnace oxidation

We have used capacitance-voltage (C-V) techniques and x-ray photoelectron spectroscopy (XPS) to study for the first time the electrical and structural properties of thin SiO2 films grown on silicon by plasma anodization and rapid thermal processes (RTO) and then compared them to furnace oxides. We have compared the SiO4 tetrahedral ring structure and the suboxide content of the ∼3-nm-thick interfacial region of these oxides and have found significant structural differences. By correlating these differences with measured electrical differences, we have identified the structural causes of some of the electrical characteristics of the plasma and RTO oxides. In plasma oxides we see larger amounts of silicon dangling bonds, Pb centers, at the Si-SiO2 interface and have identified these dangling bonds as the source of a localized peak of interface states found at 0.3 eV above the silicon valence band. Low-temperature rapid thermal annealing of the plasma oxides relieves localized compressive interfacial strain, apparently by allowing the completion of oxidation at the interface, and reduces the amount of dangling bonds. However, this strain relief simultaneously increases the average SiO4 ring structure at the interface. A larger interfacial SiO4 ring structure is also seen in rapid thermal oxides and has been attributed to the very rapid cooling which takes place at the end of the rapid thermal process. Post-growth thermal processing has been shown to reduce the average ring structure by relieving localized tensile interfacial stress, but this stress relief is accompanied by the appearance of a peak of interface states at about 0.8 eV above the valence band which is attributed to Si–O bonds broken during the anneal. Long furnace anneals of rapid thermal oxides remove these states and give interface state densities comparable to those of furnace oxides.

Ion Mixing of Near-Noble Transition Metal Films on Evaporated and Large-Grained Aluminum Substrates

ABSTRACTIon mixing experiments using Xe ions at temperatures ranging from 77K to about 450K were conducted on Al/Ni and Al/Pt couples. Evaporated polycrystalline Al films and large-grained Al crystals were used as substrates. Xenon irradiation of Al/Pt bilayers achieves considerable intermixing and a temperature dependence is observed. Only moderate interfacial mixing with little temperature dependence is observed in Al/Ni bilayers. The mixing efficiency of Al/Ni is consistent with the phenomenological model of thermal spike mixing, and so is the absence of a pronounced temperature dependence below 450K. No significant difference is noted in ion mixing of evaporated and large-grained Al substrates. In contrast to ion mixing, Al/Pt and Al/Ni samples behave similarly upon thermal annealing and form well-defined compounds. The results are also compared with Si/metal systems, where silicides can be formed readily by low temperature thermal annealing as well as by ion mixing of bilayer samples.

Control of titanium-silicon and silicon dioxide reactions by low-temperature rapid thermal annealing

Auger electron spectroscopy/depth profiling measurements demonstrate that titanium silicide forms between titanium and silicon dioxide at conventional annealing temperatures. Low-temperature rapid thermal annealing provides a process window in time and temperature to suppress this parasitic reaction relative to silicide formation at titanium-silicon interfaces within the same thin-film structure.

Characterization of the grown-in defects in Zn-doped InP

Studies of the effect of low temperature thermal annealing (170 °C) and laser annealing on grown-in defects in LEC grown Zn-doped InP have been made using the DLTS technique. One hole trap with energy of E v+∅.52 eV and density of 1.8×10∅ 15 cm −3 was observed in these InP samples. The potential well for this hole trap was determined by comparing the calculated field dependent emission rates with the field enhanced emission rate data obtained from the DLTS measurements. The results show that the potential well for this hole trap may be due to either a Dirac well or a square well, and hence the physical origin for this hole trap is attributed to either a phosphorus vacancy or a phosphorus interstitial related defect.

Study of deep-level defects and annealing effects in undoped and Sn-doped GaAs solar cells irradiated by one-MeV electrons

DLTS and C-V techniques have been employed to determine the defect energy levels and density, carrier capture cross sections, lifetimes and diffusion lengths in the Sn-doped and the undoped GaAs solar cells irradiated by one-MeV electrons under different electron fluences (10 14 to 10 16 cm −2), fluxes (2 × 10 9, 4 × 10 10 e/cm 2-s), and annealing conditions (150 ⩽ T ⩽ 230°C). The results show that density of both electron and hole traps will in general increase with incresing electron fluence and flux, and decrease with increasing annealing temperature and annealing time. Some distinct difference in defeat spectrum was observed in the undoped and the Sn-doped GaAs solar cells studied. The low temperature thermal annealing and the recombination enhanced annealing processes are found to be very effective in reducing the density of deep-level defects induced by one-MeV electrons. The results of our findings are discussed in detail in this paper.

EFFECTS OF GROWTH CONDITIONS ON DEEP-LEVEL DEFECTS IN VPE AND LPE GaAs

Studies of the deep-level defects in the VPE and LPE GaAs layers under various growth conditions have been made in this work, using DLTS and C-V techniques. In the VPE grown GaAs, characterization of grown-in defects vs. Ga/As ratio (i.e., 2/1, 3/1, 4/1, and 6/1) were made on GaAs layers grown on , , and substrates. The two common electron traps observed in these samples were due to the EB-4 (i.e., Ec -0.71 eV) level and the EL-2 (i.e., E -0.83eV) level. The density of these two electron traps was found to depend on the stoichiometry as well as substrate orientation. For examples, in the orientation samples, the density of EL2 was found to decrease with increasing Ga/As ratio (e.g., NT = 1.2x1014cm-3 for Ga/As = 2/1, and reducing to 5.4x1011 cm-3 for Ga/As = 6/1). A similar result was also observed in the EB-4 electron trap. Low temperature (230°C) thermal annealing and recombination enhanced annealing studies on these samples showed significant reduction in the density of EB-4 trap and slight reduction in EL-2 trap density. For the LPE grown GaAs layers, two growth temperatures (700 and 800°C) and two temperature dropping rates (l°C/min. and 0.4°C/min.) were used. The DLTS and C-V measurements were made on these samples, and the results showed that only EB-4 electron trap (i.e., Ec-0.71 eV) was observed in the LPE GaAs samples with 1°C/min. dropping rate. Details of our DLTS analysis of the grown-in defects vs. growth conditions in both LPE and VPE grown GaAs layers will be discussed in this paper.

Characterization of defect reduction and aluminum redistribution in silicon implanted SOS films

We report a detailed investigation of recrystallization of silicon implanted SOS films, and the effect of the recrystallization on crystalline quality and aluminum redistribution. The subsurface damage profile was generated by room temperature Si implantation. The effect of energy and dose on the damage profile was determined by channeled 2.2 MeV 4He backscatter analysis. These data were used to position the damage profile at the SOS interface. Thermal and scanned CW argon ion laser annealing were used to recrystallize the SOS films through solid state epitaxial regrowth. SIMS data are presented showing the aluminum concentration profiles before and after the silicon implants and the various anneals. High temperature annealing is shown to improve the crystalline quality, but high aluminum concentrations have been found in the silicon films. We report that laser annealing after the low temperature thermal annealing improves the crystalline quality without significant aluminum migration.

Study of grown-in defects and effect of thermal annealing in Al0.3Ga0.7As and GaAs LPE layers

Studies of the grown-in deep-level defects in the undoped n-AlxGa1-xAs (x = 0.3) and GaAs epitaxial layers prepared by the liquid phase epitaxy (LPE) techniques have been made, using DLTS, I-V and C-V measurements. The effect of 300 °C thermal annealing on the grown-in defects was investigated as a function of annealing time. The results showed that significant reduction in these grown-in defects can be achieved via low temperature thermal annealing process. The main electron and hole traps observed in the Al0.3Ga0.7As LPE layer were due to the Ec-0.31 eV and Ev+0.18 eV level, respectively, while for the GaAs LPE layer, the electron traps were due to the Ec-0.42 and 0.60 eV levels, and the hole traps were due to Ev+0.40 and 0.71 eV levels.

Deep levels in ion-implanted Si after beam annealing

Deep level transient spectroscopy has been utilized to study the electronic defect levels in cw laser-annealed and scanning electron-beam-annealed Si after ion implantation. For cw laser annealing, a dominant hole trap, whose concentration increases by more than one order of magnitude with increasing laser power, has been measured in slip-free samples. In contrast, only a low concentration of hole traps appears in electron-beam-annealed Si. This laser-induced defect is not stable at room temperature; it decays with time and can be restored by low-temperature thermal annealing. For the furnace-annealed control samples, rapid quenching from sufficiently high temperature into water produces the same defect energy level and annealing characteristic as the laser-induced defect. These annealing characteristics of laser-induced defects and thermally induced, quenched-in defects are tentatively correlated with Fe and Fe-B pair reactions in Si.

Quenched-In Defects in CW Laser-Annealed Si

ABSTRACTDLTS has been used to investigate the nature of CW laser-induced defects in ion-implanted Si. A dominant hole trap (∼Ev + 0.45 eV), whose concentration depends on laser power, was observed immediately after sample preparation. This defect is not stable at room temperature; instead, it decays as a function of time, transmuting to a shallow level at Ev + 0.10 eV. The recovery of the Ev + 0.45 eV level can be stimulated by low temperature thermal annealing or by minority carrier injection. By comparing these defects in laser-annealed samples with defects produced by furnace annealing followed by rapid cooling, and with other published results, the laser-induced defects have beenidentified as interstitial Fe and Fe-B pairs. Experiments suggest that elevated substrate temperature during laser annealing may inhibit the formation of these deep hole traps.

Effects of Low Temperature Periodic Annealing on the Deep-Level Defects in 200 KeV Proton Irradiated AlGaAs-GaAs Solar Cells

Low temperature thermal annealing (200 to 400 °C) has been shown to be effective in reducing densities of deep-level defects induced by proton irradiation in AlGaAs-GaAs solar cells. The purpose of this paper is to report our study of the effect of periodic thermal annealing on the deep level defects induced by the 200 keV proton irradiation. The AlGaAs-GaAs mesa diodes were initially irradiated at room temperature by 200 keV protons to a fluence of 1011 P/cm2, and were annealed at 200 °C, 300 °C, and 400 °C, respectively. The samples were repeatedly irradiated by the same proton fluence and then annealed at 200, 300, and 400 °C up to four irradiation and annealing cycles. The DLTS, C-V, and I-V measurements were made on these samples to determine the defect and recombination parameters as functions of proton fluence (1011 to 4×1011 P/cm2) and annealing temperature (200 to 400 °C). The results showed that densities of both electron and hole traps as well as recombination current decrease with increasing annealing temperature. For comparison, some samples were also irradiated once at a fluence of 1011, 2×1011, 3×1011, and 4×1011 P/cm2, and annealed at 200, 300, and 400 °C for six hours, respectively. No significant difference was found in defect density between the periodic and non-periodic annealed samples. The observed main electron trap was due to Ec-0.71 eV while the main hole trap was due to Ev+0.18 eV, for the 200 keV proton irradiated GaAs solar cells.

Interactions of Nonaqueous Solvents with Textile Fibers

Measurements of longitudinal shrinkage and volume swelling of polyester (PET) fibers in a wide variety of solvents were made at room temperature for time periods sufficient to establish quasiequilibrium conditions. Evaluated in terms of the solubility parameters (δ) concept, these results, together with iodine displacement studies, indicate that: (1) PET may be treated as an ( AB)x alternating copolymer, where A is a semirigid aromatic residue —CO-C 6H4— with a δ-value of 9.8, and B is a flexible aliphatic ester residue —O-CH2-CH2-O-CO— with a δ-value of 12.1 ; and (2) the preferential interaction of a solvent with either of the two PET residues provides the necessary chemical energy to disrupt intermo lecular cohesive forces between the polymer chains, permitting relaxation of internal orientation forces and shrinkage of the fiber. It is shown by successively treating PET in solvents of increasing plasticizing strength that solvent-induced crys tallization, a secondary process involving chain folding of the newly relaxed chains, does not inhibit shrinkage at lower temperatures. Therefore, room temperature chemical annealing is viewed as being similar to low-temperature (<175°C) thermal annealing, where small crystallites are formed which confer negligible dimensional stability on the fiber under going shrinkage.