Low-temperature Silicidation Research Articles

On the Challenges of SiGe HBTs in Advanced BiCMOS Technology Toward Half THz fMAX

Advanced BiCMOS technology is a cost-effective candidate for wide-range of applications, including Radar (automotive radars, high-speed industrial sensors), high-speed wireless and wireline communication, high-speed instrumentation, and mmWave THz imaging and sensing that require high performance SiGe HBTs with high cut-off frequencies fT and high maximum frequencies fMAX. Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. Vertical scaling is employed to increase fT in advanced SiGe HBTs including reduction in base and collector thickness or by increasing the collector doping. All these approaches reduce the carrier transit times, but result in an increase in the base resistance and the collector-base capacitance, which degrade fMAX. To overcome these limits, lateral scaling is necessary to reduce the base resistance and the collector-base capacitance. Reduction in emitter width reduces the intrinsic base resistance and Ccb, self-aligned emitter-base integration schemes reduce the extrinsic base link resistance, and raised extrinsic base helps with lower Rb and Ccb. In short, these scaling rules and approaches would need to reduce both base resistance and collector-base capacitance simultaneously for improved fMAX and fT In this paper, results from two experimental studies are presented in a 90nm SiGe BiCMOS technology. Compared with the baseline, one experiment shows more reduction in collector-base capacitance, while the other shows more reduction in base resistance. Both experiments achieved 300GHz fT and met or exceeded the 360GHz fMAX goal of the technology. In addition to straight vertical and lateral scaling, a series of experiments employing other process techniques and structure innovation have also been studied and are reviewed in this paper, including millisecond anneal techniques, low temperature silicide and low temperature contact processes, and secondary trench isolation, achieving fT around 300GHz and fMAX toward half THz.

High-K Metal-Gate Nanowire Junctionless FinFET with Nickel Silicide by Microwave Annealing

Background/ Objectives and Goal Silicide techniques are widely used for high-performance logic devices as the device dimensions become small towards sub-100 nm due to the source / drain sheet resistance issue.NiSiprocess has several advantages.They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance,and(6) smaller contact resistance for both n- and p-Si[1].We, therefore, propose a nickel silicide junctionlessFinFETdevices. 2. Methods Fig.1. depicts schematically view of the high-K metal-gate nanowire junctionlessFinFETwere fabricated on a 6-inch wafer with a 40 nm-thick silicon dioxide layer.The active layer with ten strips of NWs was defined by electron beam (e-beam) and transferred by reactive ion etching.An 33 nm dry SiO2 layer was grown on the active layer. Next,implanted (boron for pFETs and phosphorus for nFETs,dosage of 2 × 1014 cm2) and followed by thermal anneal in the channel.The samples were then dipped in HF solution for NWs. 3 nm of HfO2was deposited by ALD on the nanowires as gate dielectric, followed by the PVD 50 nm TiN for gate metal.After the deposition,electron beam (e-beam) defined gate contact and transferred by reactive ion etching.Next, 15 nm of titanium followed by 15 nm of nickel was deposited on the sample.NickelSilicide was formed after twice microwave anneal.First annealed by microwave with 360W for 300 sec , and1300W for 300sec. The temperature profiles versus annealing time are shown in Fig. 2[2]. 3. ExpectedResults/Conclusion/Contribution The ID–VGcharacteristics of a 15 nm gate-length high-k metal-gate nanowire junctionlessFinFET Fig. 3.The on-current value is comparableto that of a junctionlessfinfetwith the same bias conditions.In our experiment,there was no metallization past the silicide layer, therefore the resistance of the devices was large.This is the reasons why devices without silicide showed less on-current presented here. We have demonstrated high-k metal-gate nanowire junctionlessFinFET with nickel silicide fabricated with a low-temperature process.The devices have exhibited a competitive short-channel behavior and a much-improved drive current.These results indicate that silicide S/D is a promising option for a nanowire junctionlessFinFET device.We believe that this letter significantly advances the state of the art for low-temperature silicide junctionlessFinFET. REFERENCES [1] H. Iwai, T. Ohguro, and S. Ohmi, “NiSi salicide technology for scaled CMOS,” Microelectron. Eng., vol. 60, no. 1/2, pp. 157–169, Jan. 2002 [2] Y.-J. Lee et al., “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014. Figure 1

Effect of Substrate Type on CoSi2 Formation in Rapid Thermal Annealing

Low resistivity junctions and contacts are essential for fabricating high performance devices with advanced device nodes. Significant effort has been expended towards the development of low resistivity junctions. However, low resistivity contact formation has not received significant attention. The silicide of choice has been changed from high temperature silicide to low temperature silicide (i.e., WSi → TiSi2 → CoSi2 → NiSi) depending on the allowed maximum process temperature and required minimum line width for the device node. Once the candidate silicide material is chosen for the device node, relatively small improvements in resistivity and small changes in the silicide formation process have been made in recent years, despite silicidation process optimization. This includes fine tuning of silicide formation conditions for types of Si (i.e., doped poly Si, NMOS and PMOS), modifications of process steps and integration schemes. In this study, we have investigated the effect of substrate type on CoSi2 formation in rapid thermal annealing (RTA). The RTA temperature and time sensitivity of the resulting resistivity of the Co2Si contacts with P-doped poly-Si, NMOS source/drain (S/D) and PMOS S/D were investigated for process window determination using a single wafer furnace (hot wall)-based RTA system. The type of Si had a significant effect on the resulting CoSi2 formation temperature and contact resistance was observed. With the increase of RTA time, the CoSi2 formation temperature was reduced and the difference of CoSi2 formation temperature for different Si substrates became larger. Depending on CoSi2 integration schemes (i.e., one step (for all CoSi2 in poly-Si gate and S/D) or two step (one for CoSi2 for poly-Si gate and the other for CoSi2 for S/D)), the CoSi2 formation RTA conditions must be modified. Detailed effects of substrate type on CoSi2 formation and process windows will be reported. Figure 1

SiGe HBTs in 90nm BiCMOS Technology Demonstrating fT/fMAX 285GHz/475GHz through Simultaneous Reduction of Base Resistance and Extrinsic Collector Capacitance

Development of SiGe HBTs in BiCMOS technology with both high f T and f MAX faces significant challenges. To increase f T, thinning the base and collector thickness is generally the first step to reduce the carrier transit times, but this increases the base resistance and the collector-base capacitance, which impacts f MAX negatively. Increasing collector doping is also often employed to increase f T, but this increases collector-base capacitance, which drives f MAX down. To overcome these limits, millisecond anneal techniques, low temperature silicide and low temperature contact processes are employed to reduce the base resistance. Concurrently a novel approach to reduce the extrinsic collector-base capacitance is developed, without affecting the manufacturability and integration with CMOS. The simultaneous reduction of both base resistance and collector capacitance enables high performance SiGe HBT devices in 90nm BiCMOS Technology with operating frequencies of 285/475GHz f T/f MAX.

SiGe HBTs in 90nm BiCMOS Technology Demonstrating fT/fMAX 285GHz/475GHz through Simultaneous Reduction of Base Resistance and Extrinsic Collector Capacitance

Development of SiGe HBTs in BiCMOS technology with both high fT and fMAX faces significant challenges. To increase fT, thinning the base and collector thickness is generally the first step to reduce the carrier transit times, but increases the base resistance and the collector-base capacitance, which impacts fMAX negatively. Increasing collector doping is also often employed to increase fT, but again increases collector-base capacitance, which drives fMAX down. To overcome these limits, a series of process and device structure innovations have been made in recent years. Millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. A novel approach to reduce the extrinsic collector-base capacitance is developed, concurrent to the reduction of base resistance, without affecting the manufacturability and integration with CMOS. The simultaneous reduction of both base resistance and collector capacitance enables high performance SiGe HBT devices in 90nm BiCMOS Technology with operating frequencies of 285/475GHz fT/fMAX.

Characterization of Ni(Si,Ge) films on epitaxial SiGe(100) formed by microwave annealing

Microwave annealing (MWA) is investigated as an alternative technique to rapid thermal processing with halogen lamp heating (RTP) for low-temperature silicide formation on epitaxially grown Si0.81Ge0.19 layers. Phase formation, resistivity mapping, morphology analysis, and composition evaluation indicate that the formation of low-resistivity NiSi1−xGex by means of MWA occurs at temperatures about 100 °C lower than by RTP. Under similar annealing conditions, more severe strain relaxation and defect generation are therefore found in the remaining Si0.81Ge0.19 layers treated by MWA. Although silicidation by microwave heating is in essence also due to thermal effects, details in heating mechanisms differ from RTP.

Co-Induced Low-Temperature Silicidation of Ni Germanosilicide Using NiPt Alloy and the Effect of Ge Ratio on Thermal Stability

In this paper, novel Ni germanosilicide technology using NiPt alloy and Co overlayer has been proposed. Using the Co overlayer after NiPt deposition on Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> , the formation temperature of low resistive Ni germanosilicide is lowered with high thermal stability. The thermal stability of Ni germanosilicide with different Ge fraction in is also characterized. The sheet resistance degrades as increasing the Ge fraction (x) in Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> when NiPt/TiN is used. However, using the Co overlayer, the sheet resistance property among Ni germanosilicide formed with different Ge fraction is improved greatly compared with those of NiPt/TiN case (without Co overlayer). Therefore, low-temperature formation of highly thermal robust Ni germanosilicide can be achieved through the NiPt/Co/TiN tri-layer.

Thermal Stability Improvement of Ni–Germano silicide Utilizing Ni–Pd Alloy for Nanoscale CMOS Technology

In this paper, thermally stable Ni-germanosilicide technology utilizing Ni-Pd alloy and Co/TiN capping layer (Ni-Pd/Co/TiN tri-layer) is proposed for high performance strained-Si CMOS technology. The proposed Ni-germanosilicide technology exhibits low temperature silicidation with a wide temperature window for rapid thermal process (RTP). Moreover, sheet resistance shows stable characteristics in spite of the high temperature postsilicidation annealing up to 700 for 30 min. In addition, the surface of Ni-Pd/Co/TiN structure is much smoother than that of Ni/Co/TiN structure for both before and after the postsilicidation annealing. Therefore, the Ni-germanosilicide using the Ni-Pd/Co/TiN tri-layer is highly promising for future SiGe based nanoscale CMOS technology.

N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide

We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi1.8). A low-temperature silicidation process was developed for the formation of the low electron barrier height YbSi 1.8 phase, without reaction with SiO2 isolation or SiN spacer materials, enabling integration in a CMOS fabrication process flow. The fabricated device exhibits good device characteristics with a drive current of 241 muA/mum at VDS=VGS-Vt=1 V, Ion/Ioff=104 at VDS=1.1 V, subthreshold swing of 125 mV/decade, and drain-induced barrier lowering of 0.26 V/V

Sub-30 nm FinFETs with Schottky-Barrier Source/Drain Featuring Complementary Metal Silicides and Fully-Silicided Gate for P-FinFETs

AbstractWe investigated the material and electrical characteristics of platinum and ytterbium silicides for potential applications as metallic Schottky-barrier source/drain (S/D) and fully-silicided (FUSI) gate electrodes in fin field-effect transistors (FinFETs). Due to the low electro-negativity parameter of ytterbium, a low temperature silicidation process was developed to avoid the reaction of ytterbium with the isolation regions (i.e. SiO2 and SiN) to integrate ytterbium silicide successfully in mesa-isolated n-FinFETs. The integration of FUSI metal gate into p-FinFETs was also explored in this work and a novel two-step silicidation process that integrates simultaneously two different phases of platinum silicide with the appropriate work function values for gate electrode and source/drain application was demonstrated.

NiSi salicide technology for scaled CMOS

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi 2 used popularly as the silicide material has been eventually replaced by CoSi 2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi 2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi 2 and CoSi 2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

Secondary defect annihilation in ion beam processed SixGe1−x layers using titanium silicide

The secondary defect annihilation titanium silicidation in SixGe1−x layers, formed by high dose Ge implantation in (100) silicon, has been studied systematically as a function of the Ge fluence, implantation energy, and TiSi2 thickness. Rutherford backscattering spectrometry and transmission electron microscopy have been used to investigate the damaged SixGe1−x layer recovery and to monitor the germanium diffusion and reaction during the silicidation. For the highest fluence of 3×1016 Ge/cm2 (≊15 at. % Ge) it is found that nearly a complete annihilation of the secondary defects can be achieved after the first low-temperature silicidation step. After a second high-temperature silicidation step all residual defects have been removed. For fluences lower than 3×1016 Ge/cm2 a complete recovery is already obtained after the first silicidation step.

Interaction in the Cr/amorphous-silicon system

The kinetics of a low-temperature silicide formation have been investigated in experiments on the solid-phase interaction between Cr and amorphous Si (a-Si). For the Cr/plasma-enhanced chemical-vapor-deposited a-Si:H system, it was found that amorphous interlayer was formed at the interface at RT. The compositional ratio of Cr to Si in the amorphous interlayer formed at RT was found to be about 5%. On the other hand, for the Cr/sputtered a-Si system at RT, an interfacial amorphous layer with negligible thickness seemed to exist. From the experimental results and from the results previously reported, the kinetics of the low-temperature interaction were discussed and a new model of an internal-field-assisted interaction was proposed.

Ni-Si mixing: A new model for low temperature silicide formation

Ni-Si mixing: A new model for low temperature silicide formation

NiSi mixing: A new model for low temperature silicide formation

High-resolution ion backscattering has been used to study the initial stages of Ni silicide formation on Si(111). NiSi mixing is observed, following Ni deposition on clean Si(111) at room temperature, up to coverages of ∼ 8 × 10 15 Ni atoms/ cm 2. The ultra-thin mixed layers are disordered and have a composition close to Ni 2Si. Ion backscattering and high-resolution cross-section TEM observations show the films to grow out from small 3D silicide islands which are formed at the initial deposition stage. A new cluster growth model for the formation of silicide films on clean Si is derived from the results.