Low-temperature Polysilicon Process Research Articles

P‐15.1: Large Area and Low Cost Fingerprint on Display Technology

We developed a large area and low cost optical fingerprint recognition product based on LTPS (low temperature poly silicon) process. A high efficient a‐Si pin sensor is introduced, the quantum efficiency under white light is 70% and the dark state current density is E‐10 A / mm2. The “one‐to‐one” and “one to multiple” structures of sensor and micro lens are compared, and the “one‐to‐one” optical path structure is systematically analyzed and evaluated. The optical path focal length is about 100 μm. The fingerprint recognition effect is significantly improved by adding a BM shading layer, and this scheme can effectively avoid the screen burning problem caused by the high luminous intensity of pixels in the fingerprint unlocking area.

5‐3: Experimental and Physics‐Based Analysis of Leakage Currents for LTPS TFTs in AMOLED Displays

This paper presents extremely‐low leakage technologies in low‐temperature polysilicon (LTPS) TFTs. Experimental and physics‐based analysis of leakage currents, emphasizing the effects of process technologies and device design, are described. Small‐geometry TFTs, controlled by optimal LTPS process, dramatically reduce off‐state leakage current (Ioff) by suppressing gate‐induced drain leakage (GIDL) and thermal generation currents, thus potentially offering lower frame rate operations by reducing IC clock power. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate the remarkable low‐Ioff experimental results as well as more‐than‐twice enhanced on‐state current (Ion) in optimized LTPS devices.

P‐50: Study on the New Monitoring Method for Ion Implanter using Microwave Photoconductive Response in the Large Size Glass

In this paper, the advanced monitoring technology for Ion Implanter using Microwave Photoconductive Response (u‐PCR) is presented. The new monitoring method is able to be considered through the real LTPS (Low Temperature Poly Silicon) process like excimer laser annealing, ion doping and thermal activation at large size glass. The u‐PCR method expects to be able to evaluate the solid state reaction of poly silicon and substitute the present monitoring method which is manually measured a wafer doped by RTA.

P‐6.10: LTPS‐TFT Process for OLED and some issues generated from the manufacturing

AMOLED (Active‐matrix organic light emitting diode) is a new display technology used in flat panel display which has wider color gamut, higher contrast ratio, lower consumption than LCD and can achieve flexible display. However, LTPS (Low Temperature Poly‐Silicon)‐TFT (Thin Film Transistor), is now a highlight of Active Matrix Driving. As a current source, in order to drive it, there needs more TFTs and higher driven current for OLED. Compared with the traditional a‐Si TFT, LTPS‐TFT possesses the high mobility (≈100 cm2/V · s) and low off current poly‐silicon's character which is known as being high resolution ratio, quick reacting, wide aperture ratio and high integration. In this paper, we will discuss the common process of LTPS which is made in a relatively low temperature condition. Then we will talk about some display issues caused by LTPS process, such as mura, hysteresis and light spot, e.t.

UV-pretreatment- and near-infrared rapid thermal annealing-enhanced dehydrogenation for a-Si:H thin films at 400 °C

A new dehydrogenation processing method was developed for the low-temperature polysilicon process. This method can reduce both the process temperature and time through the combination of an ultraviolet pretreatment (UVP) process with near-infrared rapid thermal annealing (NIR-RTA). NIR-RTA using tungsten-halogen lamps was observed to reduce the dehydrogenation time by approximately two thirds and the temperature by approximately 20°C compared to conventional furnace processing. The UVP process was able to lower the dehydrogenation temperature by a further 20°C. Thus, the new dehydrogenation process, consisting of UVP followed by NIR-RTA, could achieve a hydrogen concentration of 1.97at.% in 20min at 360°C.

Discrete lot sizing and scheduling problem under batch processing constraints in the semiconductor manufacturing

Highly advanced technology products are manufactured on the series of equipment having various characteristics and requirements. The deposition process of organic light emitting diode, for example, is performed in chambers for a long manufacturing time, while various product devices belonging to the same family can be processed in sequence before the preventive maintenance schedule or the refill of chemical gas required. The deposition process plays as a bottleneck, and its productivity of the schedule is critical to the upstream low-temperature poly silicon process and the downstream encapsulation and module processes as well. The batch family scheduling problem is formulated using the mixed-integer programming (MIP) in consideration of the family setups, lot sizing, supplementary mask tools requirements, and material exhaustion requirements. It is shown that the planning and scheduling decisions can be made simultaneously in an integrated model, and that it can be implemented in the actual manufacturing line. Through the optimized model analysis, the capacity can be enhanced by 20∼30 % without losing the throughput and demand satisfaction as well.

Design and implementation of readout circuit on glass substrate with digital correction for touch‐panel applications

Abstract— A readout circuit on glass substrate with digital correction, which contains a transconductance amplifier, counter, and digital correction circuit, has been designed for touch‐panel applications for 3‐μm low‐temperature polysilicon (LTPS) technology. The voltage difference as a result of a change in capacitance due to a touch event is converted to current by a transconductance amplifier. By charging and discharging the capacitor in the counter, the counter displays different digital‐output codes according to touch or non‐touch events. Furthermore, not only can the touch or non‐touch event be distinguished, but also the influence of LTPS process variation can be compensated by a digital correction circuit in the proposed readout circuit.

Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications

A readout circuit on glass substrate for touch panel application has been designed and fabricated in a 3- low temperature poly-silicon (LTPS) technology. In this work, the switch-capacitor (SC) technique is applied to amplify the small voltage difference from capacitance change due to the touch event on panel. In addition, the corrected double-sampling (CDS) technique is also employed to reduce the offset originated from LTPS process variation. The minimum detectable voltage difference of the proposed circuit is 40 mV. To further identify the different touch area during touch events, a 4-bit analog-to-digital converter is used to converter the output of readout circuit into 4-bit digital codes.

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Abstract— Low‐temperature polysilicon (LTPS) technology has a tendency towards integrating all circuits on glass substrate. However, the poly‐Si TFTs suffered poor uniformity with large variations in the device characteristics due to a narrow laser process window for producing large‐grained poly‐Si TFTs. The device variation is a serious problem for circuit realization on the LCD panel, so how to design reliable on‐panel circuits is a challenge for system‐on‐panel (SOP) applications. In this work, a 6‐bit R‐string digital‐to‐analog converter (DAC) with gamma correction on glass substrate for TFT‐panel applications is proposed. The proposed circuit, which is composed of a folded R‐string circuit, a segmented digital decoder, and reordering of the decoding circuit, has been designed and fabricated in a 3‐μm LTPS technology. The area of the new proposed DAC circuit is effectively reduced to about one‐sixth compared to that of the conventional circuit for the same LTPS process.

6.2: Mechanical Properties of Jade™ Glass Substrate for LTPS Application

AbstractMechanical properties of Jade™ glass substrate, including ring‐on‐ring strength of surfaces, vertical bend strength of ground edges, dynamic fatigue constant, fracture toughness, and Young's modulus, are presented. This high strain point glass is designed to meet low compaction requirement for low temperature polysilicon process (LTPS). Its fusion surface quality ensures pristine surfaces with high strength. Its superior edge finish leads to high edge strength. Its composition and manufacturing process eliminate the need for post‐forming thermal treatment. Its intrinsic thermal stability minimizes viscous distortion during LTPS processing. Its fracture toughness is similar to that of a‐Si glasses, yet its fatigue resistance is superior due, primarily, to its composition.

Fabrication of high performance low temperature poly-silicon backplanes on metal foil for flexible active-matrix organic light emission diode displays

We have developed Low Temperature Poly-Silicon (LTPS) backplanes on metal for flexible 2.8-in. Active-Matrix Organic Light Emission Diode (AM-OLED) displays. The PMOS devices exhibit interesting characteristics such as field-effect mobility of 83 cm 2/V.s, on/off current ratio of more than 10 7, a substhreshold slope of 0.47 V/dec, and a leakage current of 0.02 pA/μm at Vds = 0.1 V. Also, thin film transistors (TFT) characteristics were shown to be very homogeneous across the plates. These good performances are attributed to the possibility of developing an LTPS process on metal very close to the process existing on glass, thanks to the use of plasma enhanced chemical vapour deposition (PECVD) SiO 2 as the thick insulator, which provides to maintain high temperature budget. The influence of the metal substrate as a back-gate was studied as a function of the insulator thickness. Based on simulation and measurements, it was evidenced that the metal potential can have a significant influence on the TFT operation. Overall, this self-aligned LTPS process on metal seems to be very promising for the manufacturing of high quality and high resolution flexible AM-OLED displays.

表面から放出される気体の分析―昇温脱離法―

Thermal desorption spectroscopy (TDS) has been commonly employed to evaluate the outgassing properties of both vacuum materials and thin films. Hydrogen, water, CO and CO2 —the most dominant gas species— can be easily detected and quantified by quadrupole mass spectrometry. This paper examines two calibration methods to convert ion current into outgassing rate: first, by using the standard leak of each gas and, second, by using an absolute pressure gauge. TDS is demonstrated for two different types of samples: stainless steel and amorphous Si (a-Si) film. In the case of stainless steel, samples blasted with glass beads were compared with chemically polished samples, and the TDS results' relationship to pumping down properties was investigated. The a-Si film examined was formed using a low temperature poly silicon process. Its hydrogen concentration as determined by TDS corresponded with that obtained by secondary ion mass spectrometry (SIMS). The outgassing temperature characteristics obtained for both the stainless steel and a-Si samples provided valuable information.

The development of a low-stress polysilicon process compatible with standard device processing

When surface micromachined devices are combined with on-chip circuitry, any high-temperature processing must be avoided to minimize the effect on active device characteristics. High-temperature stress annealing cannot be applied to these structures. This work studies the effects of deposition parameters and subsequent processing on the mechanical properties of the polysilicon film in the development of a low-strain polysilicon process, without resorting to high-temperature annealing. The films are deposited as a semi-amorphous film and then annealed, in situ at 600/spl deg/C for 1 h, to ensure the desired mechanical characteristics for both doped and undoped samples. This low temperature anneal changes the strain levels in undoped films from -250 to +1100 /spl mu//spl epsi/. The best results have been obtained for an 850/spl deg/C anneal for 30 min which is used to activate the dopant (both phosphorus and boron). No further stress annealing was used, and 850/spl deg/C does not present problems in terms of thermal budget for the electrical devices. It is shown that these mechanical characteristics are achieved by forming the grain boundaries during subsequent low temperature annealing, and not during deposition. TEM (transmission electron microscopy) studies have been used to investigate the link between the structure and mechanical strain. This has shown that it is the formation of the grain boundary rather than the grain size which has a significant effect on strain levels, contrary to reports in the literature. Using the above-mentioned deposition process, a series of experiments have been performed to establish the flexibility in subsequent processing available to the designer. Therefore, by careful consideration of the processing, a low-temperature polysilicon process, which can be used to fabricate thin micromachined structures, has been developed.

NMOS and CMOS polysilicon drive circuits for liquid crystal displays

A number of circuits that form the basic elements needed for integration of the drive circuits for active matrix LC displays have been investigated. The circuits have been fabricated using a low temperature polysilicon process and measurements have been made of the circuit performance. NMOS and CMOS circuits have been compared and while ratioed NMOS circuits have a poor performance in terms of speed and power, ratioless NMOS and CMOS circuit can both provide high-speed low-power operation.