Abstract
This paper presents extremely‐low leakage technologies in low‐temperature polysilicon (LTPS) TFTs. Experimental and physics‐based analysis of leakage currents, emphasizing the effects of process technologies and device design, are described. Small‐geometry TFTs, controlled by optimal LTPS process, dramatically reduce off‐state leakage current (Ioff) by suppressing gate‐induced drain leakage (GIDL) and thermal generation currents, thus potentially offering lower frame rate operations by reducing IC clock power. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate the remarkable low‐Ioff experimental results as well as more‐than‐twice enhanced on‐state current (Ion) in optimized LTPS devices.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
