Low-temperature Fabrication Process Research Articles

Unipolar Differential Logic for Large-Scale Integration of Flexible aIGZO Circuits

A new unipolar differential logic (UDL) for the large-scale integration of amorphous In-Ga-Zn-O (aIGZO) digital circuits is proposed. Only single-threshold single-gate and aIGZO thin-film transistors are required. The proposed UDL logic gates are very insensitive to transistor parameter variations (i.e., threshold voltage, mobility, off-current, and subthreshold slope), which are inherently due to large-area low-temperature fabrication processes and operating conditions. To assess the UDL effectiveness, a wide range of parameter variations is considered: and, owing to the proposed architecture up to 1.5 $\times$ 107 UDL gates that can be integrated with a yield that is greater than 90%.

A graphene barristor using nitrogen profile controlled ZnO Schottky contacts.

We have successfully demonstrated a graphene-ZnO:N Schottky barristor. The barrier height between graphene and ZnO:N could be modulated by a buried gate electrode in the range of 0.5-0.73 eV, and an on-off ratio of up to 107 was achieved. By using a nitrogen-doped ZnO film as a Schottky contact material, the stability problem of previously reported graphene barristors could be greatly alleviated and a facile route to build a top-down processed graphene barristor was realized with a very low heat cycle. This device will be instrumental when implementing logic functions in systems requiring high-performance logic devices fabricated with a low temperature fabrication process such as back-end integrated logic devices or flexible devices on soft substrates.

Heteroepitaxial Writing of Silicon-on-Sapphire Nanowires.

The heteroepitaxial growth of crystal silicon thin films on sapphire, usually referred to as SoS, has been a key technology for high-speed mixed-signal integrated circuits and processors. Here, we report a novel nanoscale SoS heteroepitaxial growth that resembles the in-plane writing of self-aligned silicon nanowires (SiNWs) on R-plane sapphire. During a low-temperature growth at <350 °C, compared to that required for conventional SoS fabrication at >900 °C, the bottom heterointerface cultivates crystalline Si pyramid seeds within the catalyst droplet, while the vertical SiNW/catalyst interface subsequently threads the seeds into continuous nanowires, producing self-oriented in-plane SiNWs that follow a set of crystallographic directions of the sapphire substrate. Despite the low-temperature fabrication process, the field effect transistors built on the SoS-SiNWs demonstrate a high on/off ratio of >5 × 104 and a peak hole mobility of >50 cm2/V·s. These results indicate the novel potential of deploying in-plane SoS nanowire channels in places that require high-performance nanoelectronics and optoelectronics with a drastically reduced thermal budget and a simplified manufacturing procedure.

P-Cu2O/SiOx/n-SiC/n-Si memory diode fabricated with room-temperature-sputtered n-SiC and SiOx

We investigated low-temperature fabrication processes for our previously proposed pn memory diode with a p-Cu2O/SiCxOy/n-SiC/n-Si structure having resistive nonvolatile memory and rectifying behaviors suitable for a cross-point memory array with the highest theoretical density. In previous fabrication processes, n-SiC was formed by sputtering at 1113 K, and SiCxOy and p-Cu2O were formed by the thermal oxidation of n-SiC and Cu at 1073 and 473 K, respectively. In this study, we propose a pn memory diode with a p-Cu2O/SiOx/n-SiC/n-Si structure, where n-SiC and SiOx layers are deposited by sputtering at room temperature. The proposed processes enable the fabrication of the pn memory diode at temperatures of not more than 473 K, which is used for the formation of p-Cu2O. This memory diode exhibits good nonvolatile memory and rectifying characteristics. These proposed low-temperature fabrication processes are expected to expand the range of fabrication processes applicable to current LSI fabrication processes.

Direct observation of UV-induced charge accumulation in inverted-type polymer solar cells with a TiOx layer: Microscopic elucidation of the light-soaking phenomenon

The mechanism of light-soaking phenomenon in inverted-type organic solar cells (IOSCs) with a structure of indium-tin-oxide/TiOx/P3HT:PCBM/Au was studied by electron spin resonance (ESR) spectroscopy. Charge accumulation in the cell during UV-light irradiation was observed using ESR, which was clearly correlated with the light-soaking phenomenon. The origin of the charge accumulation is clarified as holes that are deeply trapped at p-type P3HT polymer-chain ends with bromine after hole transfer from the band excitation in the TiOx layer. The holes are considered to be electrostatically attracted to trapped electrons in the TiOx layer after the band excitation. These accumulated charges are the origin of the light-soaking phenomenon. Our results strongly suggest that passivation of the residual OH groups in the TiOx layer is needed to avoid the light-soaking phenomenon by preventing electron trappings, a step that is indispensable in the operation of highly stable IOSCs without UV-light irradiation based on a low-cost and low-temperature device fabrication process using flexible plastic substrates.

Low-temperature Process for Fabrication of Porous Nanocrystalline Tin(IV) Oxide Film for Electrochromic Devices

We report a low-temperature annealing process for the fabrication of an electrochromic device based on a SnO2 nanocrystalline film. The device exhibits high transmittance and fast response times in the bleached state, and the difference in transmittance between the colored state and the bleached state is higher than that of a TiO2 film fabricated by low-temperature annealing.

Additively Manufactured Microfluidics-Based “Peel-and-Replace” RF Sensors for Wearable Applications

This paper demonstrates the first-of-its-kind additively manufactured microfluidics-based flexible RF sensor, combining microfluidics, inkjet-printing technology, and soft lithography, which could potentially enable the first “real-world” wearable “smart skin” applications. A low-cost, rapid, low-temperature, and zero-waste fabrication process is introduced, which can be used to realize complex microfluidic channel networks with virtually any type of sensing element embedded. For proof-of-concept purposes, a reusable and flexible microfluidics sensor was prototyped using this process, which only requires 0.6- $\mu {\text {L}}$ fluid volume to produce a 44% frequency shift between an empty ( $\epsilon _{r}=1$ ) and a water-filled channel ( $\epsilon _{r}=73$ ), demonstrating a sensitivity that is higher than most previously reported microfluidics-based microwave sensors. Seven different fluids were used to measure the sensitivity of the prototype and an overall sensitivity of $24\%/ \log (\epsilon _{r})$ was observed. The “peel-and-replace” capability of the presented sensor not only facilitates the cleaning process for sensor reusability, but it also enables sensitivity tunability. For bent/conformed configurations, the sensor’s functionality is good even for a bending radius down to 7 mm, demonstrating its great flexibility. After bending multiple times, the sensor still exhibits a very good performance repeatability, which verifies its reusability feature. The introduced additively manufactured RF microfluidics-based sensor would be well suited for numerous wearable and conformal fluid sensing applications (e.g., bodily fluids analyzing and food monitoring), while it could also be utilized in a variety of microfluidics-reconfigurable microwave components.

A low-temperature fabricated gate-stack structure for Ge-based MOSFET with ferromagnetic epitaxial Heusler-alloy/Ge electrodes

A possible low-temperature fabrication process of a gate-stack for Ge-based spin metal–oxide–semiconductor field-effect transistor (MOSFET) is investigated. First, since we use epitaxial ferromagnetic Heusler alloys on top of the phosphorous doped Ge epilayer as spin injector and detector, we need a dry etching process to form Heusler-alloy/n+-Ge Schottky-tunnel contacts. Next, to remove the Ge epilayers damaged by the dry etching process, the fabricated structures are dipped in a 0.03% diluted H2O2 solution. Finally, Al/SiO2/GeO2/Ge gate-stack structures are fabricated at 300 °C as a top gate-stack structure. As a result, the currents in the Ge-MOSFET fabricated here can be modulated by applying gate voltages even by using the low-temperature formed gate-stack structures. This low-temperature fabrication process can be utilized for operating Ge spin MOSFETs with a top gate electrode.

Effect of sintering temperature on adhesion of spray-on piezoelectric transducers

Abstract. Conventionally sol-gel spray-on transducers require a high-temperature (&gt; 700 °C) sintering process; however, this process can affect the microstructure of the substrate material. For mechanical elbows and valves utilized for fluid transport in the energy sector, the components are designed to have a specific microstructure, and deviations from these specifications can create weak points in the system. For this reason it is important to investigate how the temperature of the deposition process affects the substrate. This paper investigates the effect of high-temperature and low-temperature (&lt; 150 °C) processing conditions on the surface composition of the substrate. Furthermore, the resultant transducers from high- and low-temperature fabrication processes are compared to determine if a low-temperature processing method is feasible. For these studies a sol-gel spray-on process is employed to deposit piezoelectric ceramics onto a stainless-steel 316L substrate. Energy-dispersive X-ray spectroscopy is utilized to determine the composition of the substrate surface before and after transducer deposition. Results indicate that the high-temperature processing conditions may alter the surface composition of the metal due to a diffusion of the metal into the ceramic, which results in a metal surface that is bonded to the ceramic. Furthermore, it is shown that low-temperature processing of spray-on transducers is a viable method for transducer fabrication where the resultant transducers meet the industry minimum requirement of 30 dB signal-to-noise ratio. In parallel simulation calculations, finite-element method (FEM) studies were performed to model the adhesive strength of the low-temperature processed transducer to the substrate surface. Comparisons between the simulations and experiments suggest that the bond strength is much greater than the commercial gel bonds and closer to hardened epoxy glue bonds. These results indicate that spray-on transducers fabricated under low-temperature processing conditions are a viable solution for leave-in-place monitoring of structures.

Novel low-temperature fabrication process for integrated high-aspect ratio zinc oxide nanowire sensors

The authors present a new low-temperature nanowire fabrication process that allows high-aspect ratio nanowires to be readily integrated with microelectronic devices for sensor applications. This process relies on a new method of forming a close-packed array of self-assembled high-aspect-ratio nanopores in an anodized aluminum oxide (AAO) template in a thin (2.5 μm) aluminum film deposited on a silicon substrate. This technique is in sharp contrast to the traditional free-standing thick film methods, and the use of an integrated thin aluminum film greatly enhances the utility of such methods. The authors have demonstrated the method by integrating ZnO nanowires onto the metal gate of a metal-oxide-semiconductor (MOS) transistor to form an integrated chemical field-effect transistor (ChemFET) sensor structure. The novel thin film AAO process uses a novel multistage aluminum anodization, alumina barrier layer removal, ZnO atomic layer deposition (ALD), and pH controlled wet release etching. This new process selectively forms the ZnO nanowires on the aluminum gate of the transistor while maintaining the remainder of the aluminum film intact for other integrated device components and interconnects. This self-assembled high-density AAO template was selectively formed in an ultrasmooth 2.5 μm thick aluminum layer deposited through e-beam evaporation without the electropolishing required in AAO template formation in traditional 100 μm thick free standing films. The resulting nanopore AAO template consists of nanopores of 90 nm in diameter and 1 μm in height at an aerial density of 1.3 × 1010 nanopores/cm2. This thin film AAO template was then filled with ZnO using ALD at 200 °C, forming polycrystalline ZnO nanowires inside the pores. The alumina template was then removed with a buffered NaOH solution, leaving free standing ZnO nanowires of 1 μm height and 90 nm diameter, offering an increase in 38× the surface area over a standard flat ZnO film for sensing applications. The aluminum film remains intact (unanodized) in nonselected regions of the device as well as underlying the ZnO nanowires, acting as the gate of the MOS transistor. The ZnO nanowires were characterized by scanning electron microscopy, energy-dispersive x-ray spectroscopy, and transmission electron microscopy to verify stoichiometry and crystal structure. Additionally, the response of a ZnO nanowire ChemFET was measured using ammonia as a target gas. I-V characterization and transient response to ammonia in the range of 25–200 ppm were examined. The ammonia response to the threshold limit value concentration of ammonia (25 ppm) shows a 56 mV shift in threshold voltage, an overall sensitivity of 14%, an 8 min response time, and a 27 min recovery period. The ZnO nanowire fabrication sequence that the authors present is accomplished at low-temperature (&amp;lt;200 °C) and can be accomplished selectively, making it readily amenable to integration with standard metal-oxide-semiconductor field-effect transistor processing as well as other microelectronic sensors such as surface acoustic wave devices. This new process has initially been demonstrated using ZnO, but is also adaptable to a variety of nanowire materials using appropriate deposition methods as well as selective nanowire release methods. This allows the potential to conveniently fabricate a variety of high-aspect ratio nanowire based microelectronic sensors for a range of applications.

Metal-based bracken-like single-sided dye-sensitized solar cells with horizontal separation.

One of the drawbacks of typical dye-sensitized solar cells (DSCs) is their high cost and the high electrical resistance of the transparent conducting substrate. In conventional sandwich-type DSCs, only one of the FTO substrates can be replaced by a metal substrate. We investigated an all-metal-electrode single-sided DSC in which interpenetrated bracken-like Cr electrodes were created using photolithography; mesoporous TiO2 and Pt films were deposited on the laterally separated electrodes. Thermal Pt deposition and electrodeposition methods were investigated and it was found that a cyclic electrodeposition method resulted in selective Pt deposition at room temperature with a higher device performance. Cu or ZnO sacrificial layers and TiO2 or TiO2/SiO2 porous layers were used for the spacer layer that keeps the Pt electrode away from the TiO2 mesoporous layer and the optimum results were obtained when a TiO2/SiO2 layer was used. The best device had a current density of 8.47 mA cm(-2), an open circuit voltage of 0.685 V and an efficiency of 2.44%. The results of open circuit voltage decay and electrochemical impedance spectrometry showed the formation of a high-resistivity blocking layer, which was attributed to the Cr oxide formed during thermal treatment. The efficiency may be improved further by developing low-temperature fabrication processes.

Electrical properties of pseudo-single-crystalline germanium thin-film-transistors fabricated on glass substrates

By developing a low-temperature (≤300 °C) fabrication process for the gate-stack structure on Ge(111), we study electrical properties of thin film transistors (TFTs) consisting of (111)-oriented pseudo-single-crystalline-germanium (PSC-Ge) channels on glass. Although the Hall mobility (μHall) of p-type PSC-Ge layers reaches 210 cm2/V s and the gate-stack/Ge interface has low trap density, we observe field-effect-mobility (μFE) fluctuation in the p-channel TFTs from 8.2 to 71 cm2/V s, depending on the thickness of the PSC-Ge layer. Considering the μFE fluctuation and low Ion/Ioff ratio in the p-TFTs, we infer the presence of defective Ge layers near the surface of the glass substrate. This study reveals that it is quite important for the high-performance p-Ge TFTs to improve the quality of the Ge layer near the surface of the glass substrate or to choose other materials with better Ge/substrate interface qualities.

Dual-functional zinc oxide aggregates with reaction time-dependent morphology as the dye-adsorption layer for dye-sensitized solar cells

Abstract High surface area and light scattering abilities are dispensable for a well-performed photoanode of dye-sensitized solar cells (DSSCs) to respectively provide abundant active sites for dye adsorption and enhance the light path for electron excitation. In this study, an energy-saving and cost-effective low-temperature (80 °C) aqueous solution method is applied to synthesize dual-functional ZnO aggregates which are composed of small nanocrystallites with the diameter of 20 nm. The reaction time plays a significant role in controlling the morphology of ZnO nanostructures. The ZnO aggregates are randomly oriented at the early stage and the flower-like morphology gradually forms when the reaction time reaches 4 h, while the well-defined structure is further destroyed when the reaction time is increased to 8 h. The growth mechanism is proposed to discuss the formation of ZnO nanoflower. The ZnO nanoflower-based DSSC achieves a light-to-electricity conversion efficiency (η) of 4.41%, which is higher than that for the cell with commercial ZnO nanoparticles on its photoanode (3.42%) under AM 1.5G simulated sunlight with an intensity of 100 mW/cm2. The electrochemical impedance spectroscopy (EIS) is also applied to analyze the electron transport parameters to understand the kinetics of electron transport in the ZnO films. The low-temperature (150 °C) fabrication process for preparing the highly-performed ZnO film also enables the future applications of flexible DSSCs with polymeric substrates.

Growth and characterization of SiGeSn quantum well photodiodes.

We report on the fabrication and electro-optical characterization of SiGeSn multi-quantum well PIN diodes. Two types of PIN diodes, in which two and four quantum wells with well and barrier thicknesses of 10 nm each are sandwiched between B- and Sb-doped Ge-regions, were fabricated as single-mesa devices, using a low-temperature fabrication process. We discuss measurements of the diode characteristics, optical responsivity and room-temperature electroluminescence and compare with theoretical predictions from band structure calculations.

Transition metal oxides as hole-selective contacts in silicon heterojunctions solar cells

This work reports on a comparative study comprising three transition metal oxides, MoO3, WO3 and V2O5, acting as front p-type contacts for n-type crystalline silicon heterojunction solar cells. Owing to their high work functions (>5eV) and wide energy band gaps, these oxides act as transparent hole-selective contacts with semiconductive properties that are determined by oxygen-vacancy defects (MoO3−x), as confirmed by X-ray photoelectron spectroscopy. In the fabricated hybrid structures, 15nm thick transition metal oxide layers were deposited by vacuum thermal evaporation. Of all three devices, the V2O5/n-silicon heterojunction performed the best with a conversion efficiency of 15.7% and an open-circuit voltage of 606mV, followed by MoO3 (13.6%) and WO3 (12.5%). These results bring into view a new silicon heterojunction solar cell concept with advantages such as the absence of toxic dopant gases and a simplified low-temperature fabrication process.

Design and processing parameters of La2NiO4+δ-based cathode for anode-supported planar solid oxide fuel cells (SOFCs)

The Ruddlesden–Popper phase lanthanum nickelate, La2NiO4+δ (LNO), is successfully implemented as a strontium- and cobalt-free cathode in anode-supported planar solid oxide fuel cells (SOFCs) through systematic optimization of materials, processing and structural parameters. Chemical interaction between LNO and gadolinia-doped ceria (GDC), which leads to phase decomposition of composite cathode and significant deterioration of the electrochemical performance, is prevented by lowering the processing temperature below 1000 °C. For low-temperature fabrication process, the thermo-mechanical stability at the interface is secured by modifying the powder characteristics and inserting the adhesive interlayer. The issues associated with the electrical contact and current distribution are resolved by incorporating the perovskite La0.6Sr0.4CoO3−δ (LSC) as a current collecting layer, and the thermal stresses at the interface are relieved by constructing a gradient electrode structure. Consequently, the optimized anode-supported planar cell with an LNO-based cathode exhibits superior performance compared to the reference cell with a conventional cathode in the intermediate-temperature range, which is attributed to the enhanced interfacial process and surface reaction kinetics based on impedance analysis.

Crystallization of Si Templates of Controlled Shape, Size, and Orientation: Toward Micro- and Nanosubstrates

Fiber-textured polycrystalline silicon thin films have demonstrated their interest as seed layers for the epitaxial growth of high-quality materials on substrates such as glass or plastics. In the present work, we report a comprehensive study of the aluminum-induced crystallization (AIC) of isolated Si domains. Our study not only demonstrates the fabrication by AIC of shape- and size-controlled Si monocrystals at the nanoscale but also allows for the prediction of minimal annealing conditions for complete crystallization of such structures. These ultrathin [111]-oriented monocrystals are promising candidates as selected-area epitaxy substrates with both an easy control on the morphology of these structures and a low-temperature fabrication process.

Room-Temperature Fabrication of Flexible Thin-Film Lithium Batteries Based on Solid Electrolytes and Polyimide Substrates

Flexible thin-film lithium batteries can power flexible electronic devices and wearable devices. Here we report room-temperature fabrication of flexible batteries with Li/LiPON/LiFe (WO4)2 active layers on polyimide substrates by sequential magnetron sputtering and thermal evaporation. Inorganic solid electrolyte LiPON films were well prepared to achieve lithium ion conductivity of 1.794×10-6 S/cm in the composition of Li2.7P(O0.99N0.11)4. Due to two redox centers of Fe3+ and W6+ in amorphous LiFe (WO4)2 cathode films, large initial specific capacities of 115.5 μAh/(cm2-μm) and 65.4 μAh/(cm2-μm) are achieved in the flat and bending batteries respectively. After 200 cycles, the discharge capacity remains 27.6 μAh/(cm2-μm). Low-temperature fabrication process of flexible batteries insures the use of lightweight and thin polymer substrates instead of high temperature resistant metal and ceramic substrates.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Stability of Thin-Film Lithium-Ion Rechargeable Batteries Fabricated by Sputtering Method without Heating

Using only a nonheating sputtering method, all-solid-state thin-film lithium-ion rechargeable batteries composed of a Li2Mn2O4 positive electrode, Li4Ti5O12 negative electrode, and Li3PO4-xNx electrolyte were fabricated, and the stability of their electrochemical characteristics and microstructures toward charge-discharge cycling was investigated. The charge-discharge curve retained a stable S-shaped profile for the batteries with a thinner negative electrode layer, while it changed from an S-shaped profile to a two-step profile for the batteries with a thicker negative electrode layer. Transmission electron microscopy (TEM) confirmed that the diffraction rings assigned to a LiMn2O4 spinel structure sharpened after charge-discharge cycling, suggesting that more crystalline grains increased in the positive electrode during cycling. On the other hand, it was found that the shape of the interfaces of each layer was sharp and clear, and each layer nearly retained its initial structure after 100 charge-discharge cycles. Moreover, the batteries displayed stable cycle performance over more than 10000 charge-discharge cycles. The present low-temperature fabrication process may represent a great advancement in practical battery production.