Low Voltage Swing Research Articles

Low-power and area-efficient 9-transistor double-edge triggered flip-flop

Double-edge triggered flip-flops offer a solution to clock power reduction by lowering the clock frequency and maintaining the same data rate. A compact 9-transistor double-edge triggered flip-flop for reducing flip-flop power is proposed. A combination of a selective swing-based partial transmission gate (TG) approach and multi-Vt transistors is used to make it area and power-efficient. The selective swing-based transmission gate approach reduces the transistor count, and the selective use of low-Vt transistors overcomes the effect of any intermediate low swing voltage levels in the circuit due to a partial TG approach. Low transistor count reduces capacitive load of the dynamic power component, and selective use of low-Vt transistors improves circuit performance as well as reduces power-delay product. The proposed circuit is implemented in the Samsung 130nm 1P6M Multi-Vt CMOS process technology and simulated for various PVT conditions. Results show that the power consumption of the circuit is reduced by 9.58% and energy reduced by 14.2% with a 5.12% improvement in speed for a slow process when compared to the previous techniques.

Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

This paper presents the analysis of dynamic noise margin of proposed 8T static random access memory (SRAM) cell. The proposed SRAM cell has two voltage sources, one connected to the bit line and the other is connected to bitbar line. These voltage sources are used to reduce the swing voltage at the output nodes. This reduction of swing voltage causes the reduction in dynamic power dissipation of the proposed SRAM cell during switching activity. The dynamic noise margin (DNM) analysis is carried out and the results are compared with those of conventional 6T SRAM cell and existing 10T SRAM cell for different word line pulse widths. The proposed SRAM cell has higher value of DNM which ensures the higher stability than 6T and 10T SRAM cells. Simulation has been done in 65nm environment with a power supply of 1V. Microwind 3.1 is used for simulation purpose. 

Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects

We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-μm CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11× faster speeds and 1.54× lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics.

Simultaneous modification of pyrolysis and densification for low-temperature solution-processed flexible oxide thin-film transistors

High-pressure annealing (HPA) affected the thermodynamics of the formation of a solution-processed oxide film through the simultaneous modification of thermal decomposition and compression, and enabled the use of lower annealing temperatures, which was favourable for device implementation. HPA also reduced the film thickness and decreased the porosity, resulting in enhanced device characteristics at low temperature. Surface and depth profile characterization using X-ray reflectivity (XRR), X-ray photoelectron spectroscopy (XPS), time-of-flight secondary ion mass spectrometry (TOF-SIMS), and ellipsometry suggested that the HPA process supported the effective decomposition of commercial metal-nitrate and/or -salt precursors and strong bonding between oxygen and the metal ions, ultimately reducing the amount of organic residue. The as-optimized HPA process allowed for high-performance solution-processed flexible InZnO (IZO) TFTs on a polymeric substrate at 220 °C with low sub-threshold voltage swing (as low as 0.56 V dec−1), high on–off ratio of over 106, and field-effect mobility as high as 1.78 cm2 V−1 s−1, respectively. These results demonstrate that this is a simple and efficient promising approach for improving the performance of solution-processed electronic devices at low temperatures.

Effect of uniaxial strain on the subthreshold swing of ballistic carbon nanotube FETs

In this paper, using the non-equilibrium Green's function formalism (NEGF), i have investigated the effect of uniaxial strain on the subthreshold swing of the Tunneling and Schottky barrier carbon nanotube FETs. By a qualitative description of the quantum capacitance of the structures, i have shown that the uniaxial strain has strong effect on the subthreshold swing. The minimum voltage swing to obtain a given I ON/ I OFF ratio has also been investigated. The results show that, a smaller voltage swing and subthreshold swing can be obtained using a higher value of the uniaxial strain. Although a simultaneous decrease in the ON current and increase in the delay time also occurs. Hence, whenever the power consumption is the main purpose of the design, uniaxial strain can be used to achieve a very low voltage swing value.

Asynchronous Current Mode Serial Communication

An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

Low-Voltage-Driven Flexible InGaZnO Thin-Film Transistor With Small Subthreshold Swing

A flexible thin-film transistor (TFT) was made by integrating a high- HfLaO gate dielectric and an amorphous-InGaZnO (a-IGZO) active layer on a polyimide substrate. This flexible HfLaO/a-IGZO TFT exhibits a low threshold voltage of 0.1 V, a small subthreshold swing of 0.18 V/dec, a high maximum saturation mobility of 22.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V s, and an acceptable on/off current ratio of 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> . The low threshold voltage and small subthreshold swing allow the device to operate at 1.5 V for low-power applications, which should enable significant future progress in energy efficiency.

저 전력 MOS 전류모드 논리회로 설계

본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 <TEX>$16\;{\times}\;16$</TEX> 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류 모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 <TEX>$0.18\;{\mu}m$</TEX> CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다. This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The <TEX>$16{\times}16$</TEX> bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung <TEX>$0.18\;{\mu}m$</TEX> standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects

The authors propose an energy efficient error control scheme that combines simple Hamming codes with powerful product codes for deeply scaled on-chip interconnects. By using Hamming codes in low-noise environments and product codes in high-noise environments, the proposed method achieves high reliability while maintaining energy efficiency; further, hardware sharing is introduced to reduce system overhead. To achieve the same reliability in noisy environments, the proposed method uses a lower swing voltage than a conventional Hamming implementation, resulting in a 30% energy reduction; an energy reduction of up to 40% is achieved compared to a multi-error correcting BCH code.

A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS

This paper describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2 Gb/s data rate with BER < 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> across 14 cm of PCB, and also an 8.0 Gb/s data rate through 4 cm of PCB. Designed in a 1.2 V, 90 nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6 GHz. The total area of each receiver is 0.0174 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , resulting in a measured power efficiency of 0.6 mW/Gb/s.

Compact, High-Speed and Power-Efficient Electrooptic Plasmonic Modulators

CMOS compatible electrooptic plasmonic modulators are slated to be key components in chip-scale photonic circuits. In this work, we investigate detailed design and optimization protocols for electrooptic plasmonic modulators that are suitable for free-space coupling and on-chip integration. The metallic structures in the proposed devices offer simultaneous electric and optical functions. The resonance-enhanced nonlinear interaction and submicrometer-footprint of these devices meet the stringent requirements for future CMOS modulators, allowing for high-speed operation (>100 GHz) with a decent modulation depth (>3 dB) and moderate insertion loss (<3 dB) at a very low swing voltage ( approximately 1 V) and power dissipation ( approximately 1 fJ/bit). The realization of the proposed structures appears feasible with current materials and lithographic techniques.

Comparison of phase noise models on a class of ring oscillators using low voltage swing fully differential delay cells

This paper compares the phase noise models on a class of differential saturated ring oscillator with low voltage swing. Variance parameter/single stage jitter is used as the metric for comparison. When first passage time (fpt) is employed, first for the simple case of the RC representation of the differential pair, an exact expression involving the parabolic cylinder function is used in this comparison. Then for the general case, the expression using time scaling is used for comparison. On the last passage time (lpt) model, the probability distribution function (pdf) of lpt is used to further differentiate the models. The fpt part in the complete lpt pdf is identified. Comparison of the phase noise's power spectral density expression is then presented. The phase noise expression of this author does not go to infinity as offset frequency approaches zero. Finally simulation results on example designs are presented, where it is shown that the model by this author, when compared to other models, can improve accuracy by 7-10 dBc/Hz.

Characteristics of $\hbox{HfO}_{2}$ /Poly-Si Interfacial Layer on CMOS LTPS-TFTs With $\hbox{HfO}_{2}$ Gate Dielectric and $\hbox{O}_{2}$ Plasma Surface Treatment

In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO2 gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO2 /poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO2 LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO2 gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.

Designing an ultra-high-speed multiply-accumulate structure

In this article, an ultra-high-speed multiply-accumulate (MAC) structure is proposed. This fused MAC block uses low-voltage-swing (LVS) technique in the utilized carry-save adders and the final adder to improve its speed. Carry-save adders and the final adder are implemented with pass-transistor-based Manchester-carry-chain logic. Sense amplifiers are used in the output nodes to amplify the LVS signals to the standard levels of zero and one. With this technique, we achieved the outstanding clock frequency of 15GHz for a five-stage pipelined MAC, which is 87.5% higher than the highest speed achieved for a pipelined multiplier in 65nm technology and above, with the power consumption of 25mW/GHz in 1.2V voltage supply.

On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects

This paper reports a series of symmetric high performance, low to full swing level converters (udld1-converter to udld5-converter) for recovering signal levels at the receiver end of the global interconnects with large capacitive loads. The proposed udld5-converter provides a matching receiver for the up-down low swing voltage driver (UDLD) signaling style for driving the global interconnect lines. When implemented on 0.13 μm CMOS 1.2 V technology, the udld5-converter performs 16% faster, reduces the energy per switching event by 4%, the energy-delay product by 19%, and the active area by 10%, when compared with a counterpart up low swing voltage driver (ULD) level converter (uld-converter). The proposed level converter receivers, each provide a different performance energy saving trade off. The paper also provides comparative performance evaluation of the various proposed level converters and uld-converter.

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method. With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-μm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

Influence of phonon scattering on the performance of p-i-n band-to-band tunneling transistors

Power dissipation has become a major obstacle in performance scaling of modern integrated circuits and has spurred the search for devices operating at lower voltage swing. In this letter, we study p-i-n band-to-band tunneling field effect transistors taking semiconducting carbon nanotubes as the channel material. The on current of these devices is mainly limited by the tunneling barrier properties, and phonon-scattering has only a moderate effect. We show, however, that the off current is limited by phonon absorption assisted tunneling, and thus is strongly temperature dependent. Subthreshold swings below the 60mV∕decade conventional limit can be readily achieved even at room temperature. Interestingly, although subthreshold swing degrades due to the effects of phonon scattering, it remains low under practical biasing conditions.

A low voltage bootstrapped switch based on zero DC offset input voltage

This paper presents an enhancement to the bootstrapped switching circuit by improving the input range limitation for applying direct input with no dc offset voltage. Application of a Darlington pair in the structure of the conventional bootstrap circuit allows for proper operation of circuits requiring low supply voltage and direct high input swing signal with no dc offset voltage. The proposed circuit is simulated using HSPICE and 0.18µm CMOS technology. Total Harmonic Distortion (THD) measurements results in SNR values which meet the necessary performance requirements for low-voltage application of switched capacitor circuits.

저 전압 스윙 기술을 이용한 저 전력 병렬 곱셈기 설계

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16<TEX>$\times$</TEX>16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16<TEX>$\times$</TEX>16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다. This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16<TEX>$\times$</TEX>16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35<TEX>$\mu$</TEX>m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.