Low Voltage Swing Research Articles

Improving the photoswitching performance of a transistor with amorphous metal oxide semiconductor thin film by a gradient annealing approach

Metal oxides are attracting attention as electronic mate rials in research and industry. Thin films of amorphous indium gallium zinc oxide (a-IGZO) exhibit low absorbance in the visible spectrum, making them ideal components in transparent electronics. To widen the scope of use for thin film transistor (TFT) devices based on a-IGZO in on-chip sensing applications, photoresponsive behavior has been achieved by proper engineering of the active layers by either introducing a photosensitive top layer or using a method to generate localized states inside the band gap. In this paper, we propose a bilayer structured with the use of thermal annealing of a-IGZO film at different temperatures. Thermal annealing has been shown to improve the electrical performance of the TFT devices because of the improved film quality but negatively affects the photoresponsivity by removing tarp sites that play an important role in both charge generation and photomultiplication via the photogating effect. Therefore, here we propose an a-IGZO film with a high temperature-annealed bottom layer and pristine top layer. The bottom layer plays a vital role in the charge transport behavior, resulting in a low threshold voltage and subthreshold swing similar to the device with a fully annealed film, while the photoresponse of the device is driven by the higher density of gap states in the pristine top layer. This proposed method is advantageous to previously published procedures due to the simplicity of using no additional materials and complex steps to introduce trap sites into the photoactive layer, but only differential annealing temperature.

4 × 53 Gbit/s Electro-Optic Engine With a Surface-Normal Electroabsorption Modulator Array

Short-reach communication systems use electro-optic transmission engines based on low-voltage, wide bandwidth modulators to achieve high capacity and low power operation. Here, we demonstrate, for the first time, integration of a 4-channel array of surface-normal electroabsorption modulators (SNEAMs) with a 4-channel array of electronic drivers with low output voltage (~1.25-1.45 Vpp). We use this 4-channel SNEAM-driver array electro-optic engine to demonstrate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4 \times 53$ </tex-math></inline-formula> Gbit/s non-return-to-zero on-off-keying transmission across up to 2 km of standard single mode fiber over a broad wavelength range (about 26 nm), the widest band of operation achieved with SNEAMs. Integration of a SNEAM array with a low output voltage driver array, a result that we achieved thanks to the use of SNEAMs that operate with low voltage swings, represents a fundamental milestone toward the realization of optical modules based on SNEAMs.

Bias-Independent Inter-Modulation Method for Simultaneously Measuring Low-Frequency Modulation and Bias Half-Wave Voltages of Mach-Zehnder Modulators

A bias-independent inter-modulation method is proposed and demonstrated for measuring low-frequency modulation and bias half-wave voltages of Mach-Zehnder modulators (MZMs). The method consists of simultaneous sinusoidal modulation on the modulation and bias ports of the MZM under test. Sinusoidal-modulated sidebands heterodyne with each other and generate the desired inter-modulation products after photodetection, which allows extracting both the modulation depth and half-wave voltage for the modulation and bias ports of the MZM. Our method is independent of bias voltages of the MZM, which can be canceled out by carefully choosing the sinusoidal-modulation frequencies. Moreover, the proposed method enables the low swing voltage for measuring both the modulation depth and half-wave voltage of MZMs. Experiments indicate that the proposed method features the simple setup and high accuracy for low-frequency response measurement ranging from 1 Hz to 1 MHz.

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

This article introduces a 192-Gb 896-GB/s 12-high stacked third-generation high-bandwidth memory (HBM3 DRAM) with low power consumption and high-reliability traits. New design schemes and features, including internal low-voltage signaling, center strobe calibration, through-silicon via (TSV) auto-calibration, a symbol-correcting in-DRAM ECC, and machine-learning-based layout optimization, allow large amounts of data transfers among the vertically stacked base and core dies with limited delay mismatch or SI degradation, as well as reduced power consumption from low-voltage swings. Experimental results confirm 896-GB/s bandwidth operations at 1.0-V voltage conditions with up to 15% improved power efficiency.

High-Performance Indium-Gallium-Zinc-Oxide Thin-Film Transistors with Stacked Al2O3/HfO2 Dielectrics

High-performance amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs) gated by Al2O3/HfO2 stacked dielectric films are investigated. The optimized TFTs with Al2O3 (2.0 nm)/HfO2 (13 nm) stacked gate dielectrics demonstrate the best performance, including low total trap density N t, low subthreshold swing voltage, large switching ratio I ON/OFF, high mobility μ FE, and low operating voltage, equal to 1.35 × 1012 cm−2, 88 mV/dec, 5.24 × 108, 14.2 cm2/V⋅s, and 2.0 V, respectively. Furthermore, a low-voltage-operated resistor-loaded inverter has been fabricated based on such an a-IGZO TFT, showing ideal full swing characteristics and high gain of ∼27 at 3.0 V. These results indicate a-IGZO TFTs gated by optimized Al2O3/HfO2 stacked dielectrics are of great interests for low-power, high performance, and large-area display and emerging electronics.

Fabrication of Ferroelectric Gate Thin‐Film Transistors with a Lanthanum‐Doped HZO Gate Insulator and Indium‐Tin‐Oxide Channel via a Solution Process

In recent years, lanthanum‐doped hafnium–zirconium dioxide (La‐HZO) has garnered attention as a material for application in ferroelectric devices; moreover, atomic layer deposition has been applied to prepare La‐HZO films with metal–ferroelectric–metal structures. This article describes the fabrication of ferroelectric La‐HZO thin films on Pt/Ti/SiO2/Si substrates via a solution process. The dependence of the electrical properties on the La concentration of La‐HZO films annealed at 800 °C in vacuum is also discussed. The film with a La concentration of 8 at% exhibits the highest remanent polarization, whereas undoped HZO exhibits paraelectric behavior. Additionally, the leakage current of La‐HZO specimens tends to be significantly lower than that of undoped HZO. Furthermore, a higher annealing temperature corresponds to better ferroelectric properties and a lower leakage current. The characterization of fabricated ferroelectric gate thin‐film transistors (FGTs) with an 8 at% La‐HZO gate insulator and indium‐tin‐oxide channel is shown to confirm typical n‐channel transistor operation, i.e., a counterclockwise hysteresis loop in the transfer curve; this is attributable to the ferroelectric nature of the La‐HZO gate insulator. The results demonstrate that the proposed FGT design offers a low subthreshold voltage swing, high on/off drain current ratio of 106, large on‐current, and large memory window.

High Hole Mobility Inorganic Halide Perovskite Field‐Effect Transistors with Enhanced Phase Stability and Interfacial Defect Tolerance

AbstractSo far, it has been difficult to fabricate thin‐film field‐effect transistors (TFTs) based on inorganic halide perovskites (IHPs) due to their phase‐instability and uncontrollable trap density. Here, the bottom‐gate bottom‐contact structured p‐type TFTs are presented using the optimized IHP in the active layer. The stable cubic‐CsPbI3 phase is successfully synthesized by doping bismuth iodide and reduced defect densities by adding potassium bromide. The IHP TFTs based on the tailored cubic‐CsPbI3 show high hole mobility of ≈10 cm2 V−1 s−1, an on‐off current ratio of 103, and a low subthreshold swing voltage of 0.43 V dec−1. In addition, the operational stability of the fabricated device is demonstrated through the bias stress test. This study suggests that one of the key factors for fabricating an ideal p‐type IHP transistor is managing charge transport properties in the IHP layer through defect engineering.

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated end-node systems. This trend also reveals growing demands for high-speed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node System-on-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.

Indium oxide and indium-tin-oxide channel ferroelectric gate thin film transistors with yttrium doped hafnium-zirconium dioxide gate insulator prepared by chemical solution process

Ferroelectric gate transistor (FGT) with yttrium doped hafnium-zirconium dioxide (Y-HZO) gate insulator and oxide channel with various thicknesses of In2O3 and ITO were fabricated by chemical solution deposition. First, ferroelectric properties of Y-HZO in the metal-ferroelectric-semiconductor structure with 5–22 nm thick In2O3 and 6–24 nm thick ITO, have been confirmed by polarization–voltage and capacitance–voltage (C–V) characteristics. The C–V curves showed clear butterfly loops showing the depletion of In2O3 and ITO layer. Secondly, the device performance of FGTs has been evaluated with various thicknesses of In2O3 and ITO channel layer. The fabricated FGTs exhibited typical n-channel transistor operation with a counterclockwise hysteresis loop due to the ferroelectric nature of the Y-HZO-gate insulator. It was found that FGT shows a low subthreshold voltage swing, high on/off drain current ratio of 106, large on current, and memory window.

Power efficient error correction coding for on‐chip interconnection links

A configurable self-calibrated power efficient five-bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher-order error up to 9 bits with an error correction probability tolerance of 73% for on-chip interconnection links. Single error correction and double error detection with extended Hamming code (22,16) is utilised along with standard triplication error correction methods in the proposed code. Self-calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network-on-chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state-of-the-art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state-of-the-art works. The proposed code is more appropriate for on-chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.

Low-Voltage IGZO TFTs Using Solution-Deposited OTS-Modified Ta2O5 Dielectric

Low-voltage, high-performance thin film transistors (TFTs) that use amorphous metal oxide (MO) semiconductors as the active layer have been getting tremendous attention due to their essential role in future portable electronic devices and systems. However, reducing the operating voltage of these devices to or below 1 V is a very challenging task because it is very difficult to obtain low threshold voltage ( ${V}_{\text {TH}}$ ) and small subthreshold swing (SS) MO TFTs. In this article, indium gallium zinc oxide (IGZO) TFTs that use solution-deposited Ta2O5 operating at 1 V are demonstrated. To enhance the dielectric properties of the fabricated ultrathin ( ${d} \sim {22}$ nm $\pm ~2$ nm) tantalum pentoxide films, ${n}$ -octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) was used. The morphology and electrical properties of both pristine and OTS-treated Ta2O5 films have been studied. The optimized Ta2O5/OTS IGZO TFTs operate at 1 V with saturation field-effect mobility larger than 2.3 cm2/ $\text{V}\cdot \text{s}$ , threshold voltage of around 400 mV, SSs below 90 mV/dec, and current ON- OFF ratios well above $10^{{5}}$ . The performance of the presented TFTs is high enough for many commercial applications such as disposable sensors or throwaway, low-end electronics significantly reducing the cost of their production.

Analysis and design of a stacked power amplifier with 196% fractional bandwidth using equivalent circuit model

Stacked structure is a good solution to overcome the low output voltage swing provided by a single device. When several devices are stacked, the bandwidth and output power are multiple times higher. This article analyzes the small-signal voltage gain of the stacked structure, deriving the gain expression of the high-frequency model and simplified model. Based on the specific device parameter, the different small-signal voltage gains between the two models are compared and the designed stacked structure is proved to obtain a flat gain at low frequencies below about 3 GHz. To our best knowledge, this is the first article to analyze the gain flatness of stacked structure with two equivalent circuit models. To verify the stacked theory, a pseudomorphic high-electron-mobility transistor（PHEMT） power amplifier (PA) is implemented using 0.25 μm Gallium arsenide (GaAs) technology. The PA achieves an ultra-high bandwidth of 30 MHz to 3 GHz and a linear gain of 21 dB ± 1.5 dB. At a 16-V drain bias voltage, a saturated output power of higher than 2 W and a peak power-added efficiency (PAE) of 44.1% are attained.

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a serializer using the MCML-based mux-tree concept, the output of one mux at any stage is used to feed another mux at the next stage through some latch circuits, which are basically used for timing synchronization giving away penalty in terms of delay and area. The increase in number of stages of the Serializer may lead to further reduction in output swing (if common mode is not properly set), thereby causing signal integrity issues and finally loss of data. To address the same, a latency combined current mode multiplexer incorporating pMOS-based dual cross-coupled latch circuit is unearthed in this paper to further outline an area and energy efficient high-speed serializer capable of maintaining uniform peak-to-peak swing and signal quality at differential outputs. The simulations of new serializer are performed for 90-nm CMOS in the Cadence Virtuoso platform, where the average power and delay are found to be $471.6~\mu \text{W}$ and 93.9 ps, respectively, to provide a power delay product of 43.8 fJ only at a power supply of 1 V. An improved output swing of 904 mV is also noticed along with a data rate of 50 Gb/s and a BER of <10−12. The entire design is proved to be a robust one after simulating it through Monte Carlo at five different process corners and also validated at lower process nodes such as 28-nm UMC.

Analysis Of Low Power And Reliable XOR-XNOR Circuit For High Speed Applications

This paper presents a comprehensive study of different types of XOR-XNOR circuits. Our main focus is to characterise the XOR-XNOR combinational circuit design using six transistors for low power applications. The six transistor XOR-XNOR circuit can be simulated using 45nm CMOS technology in cadence virtuoso using foundry files. The simulation results demonstrates, parameters such as power, delay and power delay product(PDP) at different voltages ranging from 0.4 to 1v respectively. From the obtained results it clearly indicates the proposed design has low power consumption and full voltage swing.

An efficient and novel FDTD method based performance investigation in high-speed current-mode signaling SWCNT bundle interconnect

Carbon nanotube (CNT) has emerged as the most extensively researched area in nanoscience and amongst the frontrunners in co-triggering the nanotechnology revolution. Single-wall CNT (SWCNT) bundle is a part of CNT family and has been proposed as the future nano-wires in integrated circuits. The present paper analyzes the performance of SWCNT bundle interconnect with high-speed current-mode signaling (CMS) scheme using efficient finite-difference time-domain (FDTD) method. For the first time, FDTD based method is explored for modeling CMS SWCNT bundle interconnect incorporating practical CMOS driver gate. The CMOS gate is characterized by nth power-law model. The stability of FDTD method is ascertained by Courant condition. The proposed FDTD based method is efficient and can be used for performance analyses of future nano-wire SWCNT bundle as well as conventional copper interconnects. At the same time, this method is applicable for both traditional full-voltage swing voltage-mode signaling (VMS) and remarkable low-voltage swing CMS schemes. The various analyses in the paper reveal that CMS SWCNT bundle interconnect has higher edge over CMS copper interconnect in terms of smaller delay, lesser crosstalk induced delay and noise. The proposed analytical FDTD based method is validated using Tanner-SPICE EDA simulation tool. The maximum error between the FDTD and SPICE for the transient response in CMS SWCNT bundle interconnect for 32 nm technology node is within 3%.

Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme

An on-chip impedance self calibration methodology for LVSTL (low voltage swing termination logic) for LPDDR4 (low power double data rate) application is proposed. The proposed calibration is to compensate mismatches and variations of the transmitter output drivers due to process and temperature variations. The impedance matching concept uses process sensor and temperature monitoring sensors closely located to DQ pins as a means to detect and compensate the transistor mismatches of the output driver due to process and temperature variations. The proposed circuitry is designed with DRAM bidirectional transceiver and implemented using a 180 nm CMOS technology, and the impedance calibration technique is demonstrated with various external termination resistance of 40/48/60/80/120/240 Ω. In the receiver end, a PMOS input sense amplifier is designed considering the required common mode range for the LVSTL signal interface, and an adaptive gain control scheme is also applied on the receiver design. The process sensor is utilized to adaptively control the gain factor of the receiver. The active area including power-ring of the transmitter is 0.48 mm2 with 0.14 mm2 of the proposed calibration circuit. Since there are 32 transceivers for two channels and the channels share the calibration circuits on the same DRAM die, the area overhead is less than 1.5%. The power consumption of the calibration circuits is 160 μW with 1.8 V power supply at 180 nm CMOS technology node.

A 12-bit 1.0/2.0 GS/s Pipeline ADC in 0.18 µm SiGe BiCMOS

ABSTRACTA 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.

A variation tolerant current mode low swing signaling approach for gigascale on-chip interface circuit

Enhanced functionality per unit area is the gradually increasing demand of current manufacturing market and that desire has been fulfilled by aggressive down scaling of technology, which has adversely influenced the delay of global interconnect thereby affecting the performance of high speed design. As the time needed to charge or discharge the output node of a circuit is directly proportional to the peak-to-peak swing of the driven signal, there remains an inherent speed advantage in low swing signaling, which is considered to be one of the most suitable options to eliminate signal integrity issues in multi-gbps chip-to-chip communication. This article unveils a detailed report on the shortcomings of existing low swing signaling schemes, where no work is witnessed to generate a certain low voltage swing across any reference voltage ranging from ‘Logic 0’ to ‘Logic 1’ of the input signal. To address the same, we have come up with a novel methodology consisting of two different current sources (one at driver and the other at receiver) made of NMOS. In this case, the said reference voltage corresponds to the threshold of the receiver chip, which has to be identified at first. The simulation of proposed low swing signaling scheme is carried out using 65 nm, 45 nm and 22 nm CMOS technology to examine the performance metrics at 1.1 V supply while switching at 2 GHz. This approach does provide extensive delay and energy or PDP savings to outsmart the existing works.

Quantitative Analysis of Depletion Regime Charges in a Pristine a-Igzo TFT

Amorphous Indium Gallium Zinc Oxide (a-IGZO) based thin film transistors (TFTs) are the most suitable switching devices for flexible electronics due to their compatibility with room temperature processing with high yield, high field-effect mobility (μfe), low threshold voltage (VTH) and subthreshold swing (SS).1 Many prospective applications have been reported using metal-oxide thin-film transistors such as RFID2 and high-resolution displays3. The biggest challenges of a-IGZO TFTs are the process repeatability due to the ambient sensitivity of IGZO, for example to contamination by hydrogen, oxygen, or nitrogen, which affect device performance and reliability. It has been reported that the addition of hydrogen atoms, which act as donors, shifts the transfer characteristics negatively due to enhancing the n-type free carriers.4 On the contrary the addition of oxygen, which acts as an acceptor, shifts the transfer positively by suppressing the free carriers. In PVD deposited a-IGZO TFTs, oxygen partial pressure is a key parameter to control the turn-on voltage and field-effect mobility. Annealing either post-fabrication or mid-process can also provide controllability. Interface formation around very thin IGZO films plays a big role on performance and reliability. It is now important to investigate the quantitative measurement of charge distribution/density-of-states (DoS) in IGZO material/interfaces, especially within the depletion regime in thin-film transistors to understand any correlation between device reliability and charges in the depletion regime. Commonly positive bias stress (PBS) shifts the transfer characteristic positively. The origin is explained as the negative charge (electron) traps or migration around the interfaces. The migration process has been attributed to the transformation of the ionized positive charge state (VO 2+ + 2e-) to neutral oxygen vacancy state (VO) by capturing two free electrons. 5,6 Negative bias illumination stress (NBIS) conversely shifts the transfer characteristics negatively due to the creation/formation of positive charges (VO to VO 2+ + 2e-) in the channel region.1 In our investigation, the depletion regime interface charge, bulk charge, and DoS distribution in pristine a-IGZO devices has been quantified using electrical measurements. To do this, we added an extra contact in the IGZO TFTs at the same time as patterning the source/drain metal in a coplanar top gate device architecture. During gate voltage dependent drain current measurement, we measured the potential changes in the extra contact point (between source & drain) using a high input impedance measurement channel which directly provides information on the depletion regime charges around the interface, since the potential proportionally represents the charge. With a gate voltage of -6V and source/drain voltage of 0V the measured potential at the extra probe is -0.47V (representing a charge density in depletion regime of ~ 8.5 x 10-7 C/cm2), which gradually increased to ~0V as the gate voltage increased to -0.2V. The decrement/increment of depletion regime charges under PBS/NBIS, will provide the correct interpretation about the origin of device instabilities. For -0.2V to +6V gate voltage the extra probe channel potential depends on drain voltage and the position between the source and drain. This appears to be a very simple measurement to understand the depletion regime charges in wide bandgap amorphous metal oxide thin film transistor, which is not possible using conventional capacitance-voltage and Kelvin probe potential measurement.7

Enhanced Reliability of Vertical Strained Impact Ionization MOSFET Incorporating Dielectric Pocket for Ultra-Sensitive Biosensor Applications

Fast switching with an enhanced reliability device structure of Vertical Strained Impact Ionization MOSFET incorporating Dielectric Pocket (VESIMOS-DP) has been successfully design, simulated and analyzed in this paper. Ultra-low power with low subthreshold swing (S) and high breakdown voltage are imperative for ultra-sensitive biosensors. Impact ionization MOSFET (IMOS) is predicted to be capable of S as low as 20 mV/dec, which is much lower than Conventional MOSFET (CMOS). There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. S value for DP place at source side is higher (S 24.4 mV/decade) as compared at the drain side (S 18.9 mV/decade) intrinsic region. The vicinity of DP near the drain region reduces charge sharing effects associated with the source and thus improves impact ionization rate. The introduction of a Dielectric Pocket (DP) is believed to be able to minimize the PBT effect while improving the reliability of the device by attaining higher breakdown voltage. Consequently, with the reduced of alloy scattering, the electron mobility has been improved by 22%. In many aspects, it is revealed that the incorporation of DP enhanced the reliability of VESIMOS for future development of nanoelectronic devices.