Low Supply Voltage Applications Research Articles

A common-mode insensitive thyristor-based latch regenerative comparator for low supply voltage applications

Presented in this article is a new two-stage rail-to-rail regenerative comparator circuit designed for low supply voltage applications. This work introduces a thyristor-based latch for the first time, allowing the comparator to operate from rail-to-rail inputs. The proposed comparator has been post-layout simulated using a standard 65 nm CMOS technology. The worst-case simulation results demonstrate that the comparator exhibits a delay of less than 22ns and consumes only 132 nW of power at a supply voltage of 0.6V and a sample rate of 1 MHz across its full common-mode range. Furthermore, the total input-referred offset voltage (3std + mean) remains below 21 mV throughout the entire rail-to-rail common-mode voltage range. Compared to the conventional single-stage comparator, the proposed circuit showcases an improvement of over 87 % in terms of delay and energy efficiency. Given its dignified performance metrics, this comparator is well-suited for use in low supply voltage applications such as biomedical implants, successive approximation registers analog-to-digital converters (SAR ADCs), Internet of Things (IoT).

A rail‐to‐rail regenerative comparator with inverse inverter pre‐amplifier for low supply voltage applications

AbstractIn this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier. The proposed comparator is post‐layout simulated within a standard 180‐nm CMOS technology. In the worst‐case scenario, the energy efficiency and the delay of the comparator are improved by more than 80% compared to the conventional single‐stage comparator.

A doubled transistor latch common-mode insensitive rail-to-rail regenerative comparator for low supply voltage applications

This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants.

A High-Loop-Gain Low-Dropout Regulator with Adaptive Positive Feedback Compensation Handling 1-A Load Current

Low-dropout regulators, which have the capabilities of handling large output current and obtaining a superior transient response, are receiving increasing attention. This paper presents a high-output-current low-dropout regulator with high loop gain. An adaptive positive feedback compensation method is presented. It guarantees stability under full load conditions and achieves high loop gain. Without relying on an external zero, a ceramic capacitor with low equivalent series resistance can be employed, resulting in the minimized output voltage variation during the load transient response. In addition, the load regulation and line regulation are both small. An impedance adapting stage is inserted between the error amplifier and power transistor. It is suitable for low-supply voltage applications and drives the power transistor quickly. The simulation results indicate that the proposed LDO can supply a 1000 mA load current with a 200 mV dropout voltage. The load regulation and line regulations are 0.089 μV/mA and 0.562 m V/V, respectively. The power supply rejection is above 75 dB at 1 kHz under the full range of the output current.

Whale Inspired Optimization Algorithm for Optimal Design of Low Voltage Amplifier

This paper discusses the application of a new nature-inspired optimization algorithm, called Whale Optimization Algorithm (WOA), to the resolution and optimization of single- and multi-objective problems in microelectronic design field. The performances of WOA are tested on one of the more interesting analog integrated circuits (ICs), for low supply voltage applications, the low-voltage amplifier (LVA). After identifying and determining the constraints of the LVA circuit, WOA is used to optimize MOS transistors sizes. This allows the best gain, the largest bandwidth and the highest slew rate. These main characteristics are optimized in two ways. In the first step, each function is optimized on its own, keeping the others fixed. In the second, the three characteristics are combined, with equal weights, to form a single main objective function. WOA is coded in MATLAB and the obtained results are confifirmed by Cadence Virtuoso simulations in CMOS 0.18µm technology. The simulation results are 88.8dB (88.73dB), 23.92V/µs (20.52V/µs) and 24.6MHz (25.5MHz) for DC gain, slew rate and gain bandwidth in the single (multi)-objective experiment, respectively, justifying that WOA is an effective method for the design of the above mentioned circuit.

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Challenges and Solutions of the TFET Circuit Design

Steep sub-threshold interband tunnel field-effect transistors (TFETs) are promising candidates for low-supply voltage applications with better performance than the traditional complementary metal oxide semiconductor (CMOS). However, some of the shortcomings of TFETs also severely limit their application. From the device perspective, studies have been conducted on TFETs in order to improve their performance. Instead, this study focuses on the following four challenges from the perspective of circuit design: (1) the uncontrollable forward p-i-n current; (2) the relatively low on-current; (3) the delayed output saturation; (4) the non-shareable active area in the layout. We conduct comprehensive simulations on various circuits with TFET to analyze these four challenges. Based on the analysis results and summarization of the previous solutions, we introduce some structures and offer specific circuit design suggestions separately, not only letting the TFET circuit designer know the technologies, but also clearly showing the possible cost.

Low Voltage and High Speed Dual-Modulus Prescaler with E-TSPC Technology for Frequency Synthesizer

In this paper, a new extended true-single-phase-clock (E-TSPC) based divide-by-2/3 prescaler is proposed for low supply voltage and low power consumption applications. By using pass transistor logic and changing the logic gates, the critical path between the E-TSPC flip-flops has been reduced. Prescaler is designed by Cadence in chartered 0.18 µm CMOS process. Simulation results show that proposed dual-modulus prescaler can work up to 3.9 GHz under 0.9 V supply voltage with 226 µW power consumption and it is suitable for low power and high speed frequency synthesizer in wireless communication system.

Active DC Voltage Balancing PWM Technique for High-Power Cascaded Multilevel Converters

In this paper, a dedicated pulse width modulation (PWM) technique specifically designed for single-phase (or four wire three-phase) multilevel Cascaded H-Bridge Converters is presented. The aim of the proposed technique is to minimize the DC-Link voltage unbalance, independently from the amplitude of the DC-Link voltage reference, and compensate the switching device voltage drops and on-state resistances. Such compensation can be used to achieve an increase in the waveform quality of the converter. This is particularly useful in high-power low supply voltage applications where a low switching frequency is used. The DC-Link voltage balancing capability of the method removes the requirement for additional control loops to actively balance the DC-Link voltage on each H-Bridge, simplifying the control structure. The proposed modulation technique has been validated through the use of simulation and extensive experimental testing to confirm its effectiveness.

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired or scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs). Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low VDD operations (531 MHz at 0.6 V VDD) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 m process technology, as much as 16.4% in operation speed and 39% in power-delay-product can be achieved by the proposed design.

A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $\mu$m CMOS Technology

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 mum CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of 0 plusmn1.5 dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.

A rail-to-rail input stage with constant signal behavior in 0.12 μm CMOS

This paper introduces a new fully differential low-voltage rail-to-rail input stage structure, which possesses a constant small- and large-signal behavior over the entire input common-mode range, and is suitable for low supply voltage applications in deep-submicron technologies. The proposed input stage is fabricated with two different opamp architectures in pure digital 0.12 μm CMOS technology for experimental verification. At ±0.5 V supply, the small-signal behavior variation is 5.45% across the supply rail. The large-signal behavior is constant at different input common-mode levels. The maximum current needed for the signal behavior regulation is only 90 μA.

A novel InGaP/Al/sub x/Ga/sub 1-x/As/GaAs CEHBT

A new and interesting InGaP/Al/sub x/Ga/sub 1-x/As/GaAs composite-emitter heterojunction bipolar transistor (CEHBT) is fabricated and studied. Based on the insertion of a compositionally linear graded Al/sub x/Ga/sub 1-x/As layer, a near-continuous conduction band structure between the InGaP emitter and the GaAs base is developed. Simulation results reveal that a potential spike at the emitter/base heterointerface is completely eliminated. Experimental results show that the CEHBT exhibits good dc performances with dc current gain of 280 and greater than unity at collector current densities of J/sub C/=21kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 2.70×10/sup -5/ A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. A small collector/emitter offset voltage /spl Delta/V/sub CE/ of 80 meV is also obtained. The studied CEHBT exhibits transistor action under an extremely low collector current density (2.7×10/sup -5/ A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and useful current gains over nine decades of magnitude of collector current density. In microwave characteristics, the unity current gain cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =43.2GHz and the maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =35.1GHz are achieved for a 3×20 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> device. Consequently, the studied device shows promise for low supply voltage and low-power circuit applications.

Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6-1 V)

The DTMOS architecture is particularly suited to very low supply voltage applications (0.6-1 V). This paper presents DTMOS devices processed with a partially depleted 0.25 /spl mu/m SOI technology. It analyses their electrical behavior under total dose irradiation.

Low-voltage full-swing non-complementary BiCMOS inverters

Abstract A modified full-swing (FS) non-complementary BiCMOS inverter is described and its performance characteristics are investigated using SPICE simulations. The results obtained are compared with those of the conventional FS-BiCMOS and CMOS inverters. Ii is shown that among the three configurations investigated the proposed modified full-swing BiCMOS inverter is the most advantageous for low supply voltage applications and it guarantees speed advantages over FS-BiCMOS and CMOS inverters even at 1·5 V supply.

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 /spl mu/m BiCMOS technology.