Challenges and Solutions of the TFET Circuit Design

Abstract

Steep sub-threshold interband tunnel field-effect transistors (TFETs) are promising candidates for low-supply voltage applications with better performance than the traditional complementary metal oxide semiconductor (CMOS). However, some of the shortcomings of TFETs also severely limit their application. From the device perspective, studies have been conducted on TFETs in order to improve their performance. Instead, this study focuses on the following four challenges from the perspective of circuit design: (1) the uncontrollable forward p-i-n current; (2) the relatively low on-current; (3) the delayed output saturation; (4) the non-shareable active area in the layout. We conduct comprehensive simulations on various circuits with TFET to analyze these four challenges. Based on the analysis results and summarization of the previous solutions, we introduce some structures and offer specific circuit design suggestions separately, not only letting the TFET circuit designer know the technologies, but also clearly showing the possible cost.