Low Static Power Research Articles

Multi-peak negative differential resistance in silicene superlattice: Toward multi-valued silicene logic devices

Negative differential resistance (NDR) in two dimensional materials has been the subject of strong interest for ultra-low power nanoelectronic applications. Here, we report NDR characteristics of silicene superlattice (SL) at low bias voltages. Transport process manipulated by miniband regime for low bias region and Wannier-Stark (WS) ladders regime with multi-peak NDR for higher bias windows. Local tunneling peaks rise from hybridization of Wannier-Stark rungs in certain bias voltages. The bias position of WS states crossings down shifted with increasing device dimension leading to red shifted NDR window and increases peak to valley ratio (PVR) values. The multiple NDR windows are represented by changing the size and the number of well/barriers in silicene SL. Maximum PVR of 8 obtained for device with low height barriers. Multi-peak NDR with same PVR values in very low bias regime can find key applications in multi-valued memories with low static power dissipation.

Integration of biocompatible organic resistive memory and photoresistor for wearable image sensing application

The integration of multiple functional devices to achieve complex functions has become an essential requirement for future wearable biomedical electronic devices and systems. In this paper, we present a flexible multi-functional device composed of a biocompatible organic polymer resistive random-access memory (RRAM) and a photoresistor for wearable image sensing application. The resistive layer of organic polymer RRAM is composed by polychloro-para-xylylene (parylene-C), which is a flexible, transparent, biocompatibility and chemical stability polymer material. What is more, parylene-C is quite safe to be used within human body as it is a Food and Drug Administration (FDA)-approved material. This organic RRAM shows stable switching characteristics, low operation voltages (3.25 V for set voltage and $-$0.55 V for reset voltage), low static power consumption, high storage window and good retention properties ($>$10$^4$ s). A multi-functional device that can detect the light intensity of incident light and simultaneously store the information in the memory devices for wearable image sensing application was proposed and fabricated by integrating the organic resistive memory and a photoresistor. The threshold of incident light intensity can be easily adjust by changing the external voltage. This device is promising for building wearable electronic systems with various multiple functionalities.

Two-Dimensional MoTe­2 PN Diode and CMOS Inverter By Atomic Layer Deposition-Induced Hydrogen Doping

Recently, 2D transition metal dichalcogenides(TMDs) MoTe2 has shown outstanding properties for future electronic devices. Such TMD structures without surface dangling bonds make the 2D MoTe2 more favorable candidate than conventional 3D Si in a few nanometer scale. The band gap of thin MoTe2 appears close to that of Si and quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control charge carrier polarity of MoTe2, functional devices such as complementary metal–oxide–semiconductor (CMOS) inverter have not been reported. Here we demonstrate a 2D CMOS inverter in a single MoTe2 nanosheet by straightforward selective doping technique. In a single MoTe2 flake, initially p-doped channel was selectively converted to n-doped region with high electron mobility of 18 cm2/Vs by atomic layer deposition-induced H-doping. Our ultrathin CMOS inverter exhibited a high DC voltage gain of 29, AC gain of 18 at 1 kHz, and a low static power consumption of a few nW. Our results show a great potential of MoTe2 for future electronic devices based on 2D semiconducting materials Figure 1

Express Read in MLC Phase Change Memories

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and capability of storing more than one bit per cell (multilevel cell, or MLC). However, the short lifetime and long access latency of PCM (specifically MLC PCM) require feasible and efficient solutions. In this article, based on the observation that applications access a significant number of read-friendly data blocks, we propose Express Read to prevent the MLC PCM read circuit to spend unnecessary time sensing the cells of a memory block. A read-friendly data block (RFDB) is composed of only “11” and “00” bit pairs, and thus upon sensing the most significant bit of a cell, the read operation can be early terminated to reduce the MLC read time and power consumption. Moreover, we increase the number of RFDBs using two simple techniques to better exploit the benefits of Express Read. Results obtained from full-system simulation near 6% performance improvement and 21% energy gain, on average, over the baseline system.

Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory

Phase change memory (PCM) has emerged as a new main memory in embedded systems because of its attractive characteristics, which include a lower static power, higher density, byte-addressability, and non-volatility. Although PCM has various advantages, it has a longer write latency than dynamic random access memory (DRAM) and limits the write endurance in each cell. Recently, a hybrid main memory was designed that combined DRAM and PCM. In particular, the page replacement policy in this hybrid main memory has been one of the major areas of study. The previous page replacement policies had three problems when used in embedded systems: the allocation policy, read/write access pattern identification, and migration policy. This paper proposes the adaptive-classification CLOCK (AC-CLOCK) page replacement policy for the hybrid main memory of an embedded system. AC-CLOCK measures the read/write access patterns of application programs and reduces the number of write operations in PCM by tracing these patterns. In addition, it reduces the number of unnecessary page migrations from PCM to DRAM by tracking the detailed access patterns such as write intensive pages or read intensive pages. In our experiments, AC-CLOCK reduced the number of write operations in PCM by 57.87% on average and outperformed the hit ratio of write operations in the DRAM by 9.47% on average, compared with CLOCK, CLOCK-Pro, and CLOCK-DWF. Moreover, AC-CLOCK reduced the energy delay product (EDP) by 23.25% on average, compared with the previous techniques.

Memristor-CNTFET based ternary logic gates

Multilevel electronic systems offer the reduction of implementation’ complexity, power consumption, and area. Ternary system is a very promising system where more information is represented in the same number of digits compared to the binary systems. In this paper, ternary logic gates and some of their ternary circuit applications are presented using memristors and CNTFET inverter. This integration between memristors and CNTFET offers low static power, small area and high performance. The proposed circuits do not require refreshment like the previously published circuits and are not initial state dependent because the memristors switch between the low resistance and high resistance states according to each input. In addition, we investigate the mathematical analysis of the proposed memristor ternary logic gates circuits. In the circuit simulations, a VTEAM model is used to verify the proposed circuits. Finally, a comparison between the proposed circuits with the previously published implementations is discussed showing better performance in terms of power, delay and area.

A 13.56 MHz CMOS High-Efficiency Active Rectifier With Dynamically Controllable Comparator for Biomedical Wireless Power Transfer Systems

A 13.56-MHz active rectifier with a dynamically controllable common-gate comparator for wirelessly powered supplied implantable medical devices is presented in this paper. The proposed active rectifier is composed of two comparator-controlled PMOS and two cross-coupled NMOS for achieving high-voltage and high-power conversion efficiency. The dynamically controllable common-gate comparator is implemented for high input level and low static power consumption of the rectifier. An active self-body bias is implemented to eliminate the body effect of the power PMOS. An SR latch is adopted for the comparator to control the offset and to stabilize the output pulse. The proposed rectifier is fabricated in a standard 0.13- $\mu \text{m}$ (3.3-V device) CMOS process with 0.102-mm2 active area. The measured input and output ranges under 500- $\Omega $ output load are 2.14–3.6 V and 2–3.46 V, respectively. The measured power conversion efficiencies versus output load (0.1–1 ${\text{k}}\Omega $ ) under 3.6 V ac input are 88%–91.9%, and the voltage conversion efficiencies are 86%–96.4%.

Novel electronic structures and enhanced optical properties of boron phosphide/blue phosphorene and F4TCNQ/blue phosphorene heterostructures: a DFT + NEGF study.

Blue phosphorene (Blue-p), an allotrope of black phosphorene, has attracted extensive interest due to its hexagonal crystal with a flat arranged layer of phosphorus atoms. However, the indirect band gap of Blue-p greatly hinders its applications in optoelectronics. By stacking both boron phosphide (BP) and the organic molecule 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ) with Blue-p, we construct BP/Blue-p and F4TCNQ/Blue-p heterostructures. We reveal that the BP/Blue-p heterostructure possesses a direct band gap of 0.605 eV and is tunable via in-plane strain and an external electric field. Moreover, it also has remarkable optical absorption in the UV region and enhanced transport properties. Furthermore, by doping with F4TCNQ, the F4TCNQ/Blue-p heterojunction displays type-II semiconducting properties with a flat valence band and Van Hove singularities at the Fermi level, which can be used to achieve extremely low in-band tunneling, yielding low static power dissipation and large drive currents in the ON regime of transistors. Due to the superior electronic, optical and transport properties, Blue-p-based heterostructures are promising candidates for electronic and optical device applications.

Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.

Homogeneous 2D MoTe2 p-n Junctions and CMOS Inverters formed by Atomic-Layer-Deposition-Induced Doping.

Recently, α-MoTe2 , a 2D transition-metal dichalcogenide (TMD), has shown outstanding properties, aiming at future electronic devices. Such TMD structures without surface dangling bonds make the 2D α-MoTe2 a more favorable candidate than conventional 3D Si on the scale of a few nanometers. The bandgap of thin α-MoTe2 appears close to that of Si and is quite smaller than those of other typical TMD semiconductors. Even though there have been a few attempts to control the charge-carrier polarity of MoTe2 , functional devices such as p-n junction or complementary metal-oxide-semiconductor (CMOS) inverters have not been reported. Here, we demonstrate a 2D CMOS inverter and p-n junction diode in a single α-MoTe2 nanosheet by a straightforward selective doping technique. In a single α-MoTe2 flake, an initially p-doped channel is selectively converted to an n-doped region with high electron mobility of 18 cm2 V-1 s-1 by atomic-layer-deposition-induced H-doping. The ultrathin CMOS inverter exhibits a high DC voltage gain of 29, an AC gain of 18 at 1 kHz, and a low static power consumption of a few nanowatts. The results show a great potential of α-MoTe2 for future electronic devices based on 2D semiconducting materials.

Highly robust asymmetrical 9T SRAM with trimode MTCOS technique

Memory design is the most complex part of any electronic devices. There are many parameters either intrinsic or extrinsic effects the system. In the memory design some features should be focus like stability, leakage current and delay. These parameters play important role in terms of performance. There is a lot of degradation in performance while not using the system. In this paper we used MTCMOS tech for optimizing parameters like stability static power dissipation and delay. We characterized the parameters of conventional 6T, Asym8T Asym 9T. The main focus is on the Asym 9T because it had low static power dissipation low delay and high stability. We simulated Asym 9T on different values of the threshold values and β values. Asym 9T SRAM cell exhibits high stability with dual threshold voltage.

Sub‐threshold level converter with internal supply feedback for multi‐voltage applications

A new sub-threshold level shifter for ultra-low voltage digital systems is presented in this study. The self-controlled supply feedback loop is quintessential for this circuit. Measured results from a test chip show that it is capable of realising a voltage conversion from a voltage as low as 0.1-1.2 V reliably, while maintaining an operational frequency of 25.2 kHz, when implemented in a 65-nm process technology. In addition, it also has ample process variation tolerance and low static power consumption. To support multi-voltage digital systems, the proposed level converter can up-convert an input at any voltage with this range to normal voltage domains.

Research of reactive power control strategy to reduce the reactive power exchange of AC and DC power grid

In order to solve the difficulties of steady-state voltage regulating for ac power grid brought about by surplus reactive power during the small power running for dc project, the general practice is by adding station low reactor or static reactive power compensator to absorb surplus reactive power, or by adjusting the operation mode of ac/dc system to change converter consumption of reactive power, realising the balance of reactive power exchange. Via the detailed analysis and research of auxiliary converter reactive power control strategy (converter and low load reactive power optimisation function) based on different technical route of dc control system, deducing the relation between the converter reactive power consumption and α / γ , current, which show that increasing minimum γ can absorb surplus reactive power, effectively solving ac grid voltage rise during small power running. At the same time, engineering widely used for a low reactor or static reactive power compensator adopted in weak ac system with reactive power balance control strategy are discussed, putting forward the feasible suggestions of reactive power optimisation control strategy to reduce ac/dc power grid reactive power exchange. Experiments proved that the proposed method can effectively solve the surplus reactive power problem during dc low power operation, simplify the converter station reactive power configuration, can be applied in dc project, and has good applicability.

A novel high efficiency CMOS RF/DC power harvester based on constant on/off time buck controller for 60GHz frequency band

A novel 60 GHz RF/DC power harvesting system is presented. The system consists of RF to DC rectifier and a DC/DC Buck converter based on constant ON/OFF time (COOT) control. The rectifier has a structure of voltage doubler, but employs diodes that have lower parasitics compared to those of the standard MOSFET diodes, resulting in improved power conversion efficiency. The peak efficiency of the rectifier obtained with the extracted parasitics for the output power of 1 mW is about 25%. In order to keep the output voltage of the system to 1.2 V, the COOT control in the Buck converter is used. COOT control has much better efficiency at low output powers compared to the PWM systems. For correct operation of the COOT control, auxiliary sub-blocks: a low power high-speed comparator, a hysteresis comparator, and a high-speed voltage reference are designed and presented. The maximum switching frequency in the Buck converter is about 100MHz and the whole control system has very low static power consumption. The efficiency of the overall system for the output power of 1mW is about 21%. The system is designed in 65 nm CMOS technology.

An Ultralow-Voltage Energy-Efficient Level Shifter

This brief presents an energy-efficient level shifter (LS) able to convert extremely low level input voltages to the nominal voltage domain. To obtain low static power consumption, the proposed architecture is based on the single-stage differential-cascode-voltage-switch scheme. Moreover, it exploits self-adapting pull-up networks to increase the switching speed and to reduce the dynamic energy consumption, while a split input inverting buffer is used as the output stage to further improve energy efficiency. When implemented in a commercial 180-nm CMOS process, the proposed design can up-convert from the deep subthreshold regime (sub-100 mV) to the nominal supply voltage (1.8 V). For the target voltage level conversion from 0.4 to 1.8 V, our LS exhibits an average propagation delay of 31.7 ns, an average static power of less than 60 pW, and an energy per transition of 173 fJ, as experimentally measured across the test chips.

Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes

Optical interconnects for system-in-package applications can be designed for various bit rates. In this paper, an optimization study is conducted to find the optimal parameters for electrooptical links, based on a silicon photonic technology. We focus on the bit rate to achieve highest possible power efficiencies. This paper takes all the elements of an electrooptical link into account: serialization stage, ring-resonator-based modulator, thermal stabilization, modulator driver, laser, receiver, deserialization stage, and clock-phase generation. The optimization is based on a simulation-supported database for single-ended transimpedance amplifiers (TIAs). For all the other, elements of the link simulation-based power consumption models are presented. Furthermore, an analytical solution for the TIA bandwidth and bit rate relationship is derived based on the system jitter, the TIA noise, transimpedance, bandwidth and minimal output swing, and the available input signal. Optimal bit rates are derived and discussed for a 65-nm CMOS and a 28-nm fully depleted silicon-on-insulator technology. We found that the optimal bit rates increase with more aggressive technology scaling and smaller photodiode capacitances, but decrease if lower static power consumptions can be achieved (e.g., by efficient thermal tuning of ring-resonator modulators). We conclude that further research should aim for lower tuning powers instead of higher speed.

High-performance heterogeneous complementary inverters based on n-channel MoS2 and p-channel SWCNT transistors

Heterogeneous complementary inverters composed of bi-layer molybdenum disulfide (MoS2) and single-walled carbon-nanotube (SWCNT) networks are designed, and n-type MoS2/p-type SWCNT inverters are fabricated with a backgated structure. Field-effect transistors (FETs) based on the MoS2 and SWCNT networks show high electrical performance with large ON/OFF ratios up to 106 and 105 for MoS2 and SWCNT, respectively. The MoS2/SWCNT complementary inverters exhibit Vin-Vout signal matching and achieve excellent performances with a high peak voltage gain of 15, a low static-power consumption of a few nanowatts, and a high noise margin of 0.45VDD, which are suitable for future logic-circuit applications. The inverter performances are affected by the channel width-to-length ratios (W/L) of the MoS2-FETs and SWCNT-FETs. Therefore, W/L should be optimized to achieve a tradeoff between the gain and the power consumption.

Orthogonal Ambipolar Semiconductor Nanostructures for Complementary Logic Gates.

We report orthogonal ambipolar semiconductors that exhibit hole and electron transport in perpendicular directions based on aligned films of nanocrystalline "shish-kebabs" containing poly(3-hexylthiophene) (P3HT) and N,N'-di-n-octyl-3,4,9,10-perylenetetracarboxylic diimide (PDI) as p- and n-type components, respectively. Polarized optical microscopy, scanning electron microscopy, and X-ray diffraction measurements reveal a high degree of in-plane alignment. Relying on the orientation of interdigitated electrodes to enable efficient charge transport from either the respective p- or n-channel materials, we demonstrate semiconductor films with high anisotropy in the sign of charge carriers. Films of these aligned crystalline semiconductors were used to fabricate complementary inverter devices, which exhibited good switching behavior and a high noise margin of 80% of 1/2 Vdd. Moreover, complementary "NAND" and "NOR" logic gates were fabricated and found to exhibit excellent voltage transfer characteristics and low static power consumption. The ability to optimize the performance of these devices, simply by adjusting the solution concentrations of P3HT and PDI, makes this a simple and versatile method for preparing ambipolar organic semiconductor devices and high-performance logic gates. Further, we demonstrate that this method can also be applied to mixtures of PDI with another conjugated polymer, poly[2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene]) (PBTTT), with better hole transport characteristics than P3HT, opening the door to orthogonal ambipolar semiconductors with higher performance.

Exploration of trade-offs in the design of volatile STT–RAM cache

Abstract STT–RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT–RAM is inefficient in terms of energy and speed compared to SRAM and thus various device-/circuit-/architecture-level solutions have been proposed to tackle this inefficiency. One of the proposed solutions is redesigning STT–RAM cell for better write characteristics at the cost of shortened retention time (volatile STT–RAM). Because the retention failure of STT–RAM has a stochastic property, an extra overhead of periodic scrubbing with error correcting code (ECC) is required to tolerate the failure. The more frequent scrubbing and stronger ECC are used, the shorter retention time is allowed. With an analysis based on analytic STT–RAM model, we have conducted extensive experiments on various volatile STT–RAM cache design parameters including scrubbing period, ECC strength, and target failure rate. The experimental results show the impact of the parameter variations on last-level cache energy and performance and provide a guideline for designing a volatile STT–RAM with ECC and scrubbing.

Resistive switching characteristics and mechanisms in silicon oxide memory devices

Abstract Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)–compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.