Low Specific Contact Resistance Research Articles

Low Resistance Ohmic Contact on Epitaxial MOVPE Grown β-Ga2O3 and β-(AlxGa1−x)2O3 Films

We report on the realization of record low resistance Ohmic contacts to MOVPE-grown heavily Si-doped $\beta$-Ga$_2$O$_3$ and $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$ epitaxial films. Transfer length measurement (TLM) patterns were fabricated on the heavily Si-doped homoepitaxial $\beta$-Ga$_2$O$_3$ films with electron concentration (n) ranging from 1.77 to 3.23e20 cm^-3. Record low specific contact resistance and total contact resistance (Rc) of 1.62e-7 Ohm.cm^2 and 0.023 Ohm.mm were realized for $\beta$-Ga$_2$O$_3$: Si films with n > 3e20 cm^-3. TLM structures were also fabricated on heavily Si doped coherently strained $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$ (x=12%, 17% and 22%) films. The film with 12% Al composition (n=1.23e20 cm^-3) showed \r{ho}c of 5.85e-6 Ohm.cm^2, but it increased to 2.19e-4 Ohm.cm^2 for a layer with a 22% Al composition. Annealing the samples post metal deposition has generally led to a decrease in contact resistance, but for high Al content $\beta$-(Al$_x$Ga$_1-x$)$_2$ O$_3$, the contact resistance did not change significantly after the annealing process. The low contact resistance values measured in this work are very promising for the fabrication of high frequency power devices.

Low Specific Contact Resistivity of 10−3Ω·cm2 for Ti/Al/Ni/Au Multilayer Metals on SI-GaN:Fe Substrate

For the application of third-generation compound semiconductors based on high-voltage, high-power, and high-frequency devices, particularly in photoconductive semiconductor switches (PCSSs), the ohmic contact preparation technology on semi-insulating substrates is crucial. However, iron-doped semi-insulating gallium nitride (SI-GaN:Fe) with low carrier concentration and high bulk resistivity has a very difficult time achieving good ohmic contact characteristics. Here, we have demonstrated preliminary results on an interesting class of good ohmic contact of Ti/Al/Ni/Au on Ga-face of SI-GaN:Fe. The results indicated that the Ti and Al thickness ratio is a critical parameter when determining the optimum annealing temperature and time for ohmic contact. With alloyed Ti/Al/Ni/Au stacks of 20 nm/120 nm/55 nm/45 nm on SI-GaN:Fe after annealing at 850 °C for 35 s in N2 atmosphere, a low specific contact resistivity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-3}\,\,\Omega \cdot $ </tex-math></inline-formula> cm2 is achieved. At a future date, such excellent ohmic contact characteristics can be applied to the SI-GaN:Fe-based high-power PCSS.

Bismuth telluride based efficient thermoelectric power generator with electrically conducive interfaces for harvesting low-temperature heat

Nearly 50% of the heat released by various sources in the environment is found in the temperature range below 573 K. Thermoelectric generators (TEGs) offer a robust solid-state energy conversion mechanism to harvest this waste heat into useful electrical energy. To develop efficient TEGs, a prerequisite is to couple n - and p -type thermoelectric materials through metallic interconnect, with low specific contact resistivity ( ρ c ). The realization of low ρ c involves several critical factors, such as the chemical and mechanical stability, which should be carefully optimized to achieve consistent TEG performance under long-term operation. In the present work, we have demonstrated the concept of a graded interface layer to realize electrically conducive contacts in mechanically alloyed n -Bi 2 Te 2.7 Se 0.3 and p -Bi 0.5 Sb 1.5 Te 3 thermoelectric material (TM) having moderate figure-of-merit ( zT ). We have reproducibly achieved electric contacts with low ρ c in these materials (∼59-71 μΩ-cm 2 ) using a graded layer of Ni. Using the established approach, the conversion efficiency ( η exp ) of 6.5% (±10%) is demonstrated for the temperature difference (Δ T ) of 270 K. Achieved η exp in the present work matches well with the simulated conversion efficiency ( η sim )∼7.0%, and is one amongst the best-reported efficiencies surpassing the state-of-the-art commercial modules.

Thermally stable and conductive nickel-incorporated gallium oxide thin-film electrode for efficient GaN microscale light-emitting diode arrays

Microscale light-emitting diodes (µLEDs) have attracted considerable attention as next-generation solid-state lighting sources owing to their reliable performance and attractive properties, such as easy miniaturization and stable operation in various movements. However, the quantum efficiency of μLEDs is lower than that of larger-size LEDs, which hinders their use in high-performance μLED display applications. Herein, a thermally stable and highly conductive GaOx thin-film as a p-type contact electrode is demonstrated by using electric-field-induced doping treatment (EDT) to achieve high-performance GaN µLEDs. The proposed GaOx electrode exhibits high transmittance (92%) and low specific contact resistance (3.5 × 10-3 Ωcm2), along with high thermal stability (over 10 years at 77 °C). Transmission electron microscopy analyses show that conductive channels are formed in the GaOx electrode based on the diffusion of metallic Ni species from the top metal because of EDT, thereby facilitating efficient hole injection into the μLED pixels with little spreading to the passivation layers. Consequently, the µLED array with the GaOx electrode exhibited a 12% higher light output power and 57% higher current level than those of a µLED array with conventional ITO electrodes. The results of this study can guide efforts dedicated to further improving the performance of ITO-based optoelectronic devices, including µLEDs.

Transparent Conductive Oxide (TCO) Gated Ingaas Mosfets for Front-Side Illuminated Short-Wave Infrared Detection

TCO gated InGaAs MOSFETs are demonstrated as a high responsivity and broadband short-wave infrared (SWIR) photodetector under front-side illumination (FSI). InGaAs MOSFET structures have many advantages for monolithic integration with optical communication devices with O, C, and L bands and Si-LSI.The TCO gated InGaAs MOSFETs were fabricated through the gate-last method as shown in Fig. (a) [1]. A 300-nm-thick p-type In0.53Ga0.47As layer was grown on an InP (001) wafer using MOCVD. After the deposition of a 10-nm-thick Al2O3 protection layer by ALD, the InGaAs active region was defined by chemical wet etching for mesa isolation. For the formation of the source/drain region, Si ions were implanted with 2×1014 cm-2 at 15 keV, followed by RTA at 450 °C for 10 min to achieve dopant activation. After splitting the Al2O3 protection layer, a 10-nm-thick Al2O3 gate oxide layer was deposited again. As TCO gate, Ce and H co-doped In2O3 (In2O3: Ce, H) with an electron mobility of ~160 cm2/V·s and a carrier density of ~ 2×1020 cm-3 were used [2, 3]. The amorphous TCO gate, which were deposited onto the Al2O3 layer using the ion plating method, were lifted off and crystallized by annealing at 250 °C for 30 min. Finally, Ti/Au formed for the S/D and gate contact after post-metallization annealing (PMA) at 250 °C for 30 min.The thin TCO films exhibited a very low specific contact resistance of 9.01 × 10-8 W·cm2 and a sheet resistance of 18.7W/sq. We confirmed the normal n-channel MOSFET operation with an I on/I off ratio of > 1×104. S.S. and D it values were 134 mV/dec. and 5.2 × 1012 eV-1cm-2, respectively. The peak G m was observed at V G= 0.5 V, and the extracted peak field-effect mobility was 620 cm2/V·s. The threshold voltage negatively shifted to -0.38 V, operating in enhancement mode owing to the work function of the TCO (4.2 eV), which is smaller than the Fermi level energy of p-type InGaAs (5.09 eV).Figure (b) shows the I D - V G characteristics of InGaAs MOSFETs at V G = 1 V in the dark and under illumination at the excitation wavelength of 1550 nm with an incident optical power of 5213 nW. SWIR light was illuminated in the channel area (L/W = 10 μm/10 μm) of TCO gated InGaAs MOSFET with a spot size of 10 μm. Under SWIR illumination, an increase in can be observed in the entire gate bias. Owing to the normally-on operation of the TCO gated InGaAs MOSFET, a photocurrent is detected even if the gate bias is 0 V. The photocurrent increased with the gate bias and reached the maximum in the vicinity of V G = 0.5 V, which corresponds to that of the maximum transconductance. The primary photo-response when the device is under illumination is known as the photovoltaic effect [4, 5]. The photo-generated holes move to the source region and accumulate at the potential barrier between the source and the channel. This results in the effective reduction of a potential barrier for electrons at the source edge. These phenomena lead to a decline in the threshold voltage of the MOSFET, which leads to the increase of the drain current. The threshold voltage of the TCO gated InGaAs MOSFETs in the dark was -0.35 V, and this value shifted to -0.45 V under illumination. Because is proportional to the mobility at the MOS interface, the improvement of the interface quality of the TCO/Al2O3/InGaAs MOS structures can enhance the sensitivity.Owing to the SWIR transparent TCO, we observed a responsivity of more than 1 A/W in the range of 1000 nm to 1800 nm, which includes the entire optical communication wavelength bands (1260–1625 nm). Because the maximum sensitivity of InGaAs photodiode was approximately 1 A/W at approximately 1550 nm [6], it is demonstrated that TCO gated InGaAs MOSFETs is a highly sensitive device in the SWIR region owing to the gain mechanism in the photoFETs.[1] T. Maeda, et al., Appl. Phys. Lett., 119, 192101 (2021).[2] T. Koida, et al., Status Solidi A, 215, 1700506 (2018).[3] T. Koida, et al., Status Solidi A, 218, 2000487 (2021).[5] Y. Takanashi, et al., IEEE Electro. Dev. Lett., 19, 472 (1998).[6] http://www.thorlabs.com. Figure 1

Two‐Dimensional Tellurene Transistors with Low Contact Resistance and Self‐Aligned Catalytic Thinning Process

AbstractTwo‐dimensional (2D) tellurene (Te) has shown its great potential in nanoelectronics for its high carrier mobility and air stability. However, the high‐resistance electrical contact and relatively thick Te channel hinder its ultimate scaling and device performance. Here, the transport property of Te field‐effect transistors using platinum (Pt) contact with high work function is studied, which facilitates the effective hole injection in the p‐type Te channel. The electrical contact to Te using the Y‐function method (YFM) and the transmission line method (TLM) is investigated. The Te transistors with Pt contact show a low contact resistance of 400 Ωµm, a short transfer length of 80 nm, and low specific contact resistivity of 3.2 × 10−7 Ωcm2, resulting from the low Schottky barrier height (SBH) of Pt/Te interface. The Pt electrode also can work as an efficient catalyst that allows reduction of the Te channel thickness with a controllable thinning process in water under white light illumination. This self‐aligned catalytic thinning process enables the construction of the transistors with a thin Te channel and thick Te contact with Pt metal electrodes, which provides a device configuration with both effective electrostatic control and low contact resistance.

A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

A systematic germanium (Ge) and vanadium (V) study on 4H-SiC epitaxial layers is presented. Electrical results of TLM structures which were fabricated on these layers revealed that highly-doped Ge and V-implanted layers showed extremely low specific contact resistivity, down to 2 x 10-7 Ω.cm2. Current flow in the conducting state of Schottky barrier diodes has been successfully suppressed in some implanted layers, with highly V doped samples showing current density values of approximately 1 x 10-5 Acm-2 at 10 V. DLTS spectra reveal the presence of germanium and vanadium centers in the respective samples as well as novel peaks which are likely related to the formation of a novel GeN center.

Mechanism of low Ohmic contact resistance to p-type GaN by suppressed edge dislocations

In this paper, an excellent Ohmic contact to p-GaN with a low specific contact resistance (ρc) of 2.0 × 10−5 Ω·cm2 is demonstrated using a patterned sapphire substrate (PSS) and oxidized Ni/Au contacts. GaN epitaxy with high crystal quality on the PSS, confirmed by high-resolution x-ray diffraction, played a key role in the improved Ohmic contact to p-GaN. The edge dislocations were annihilated during the epitaxial process on the PSS to afford a low surface dislocation density, which was in accordance with the results of transmission electron microscopy and cathodoluminescence spectroscopy. Furthermore, a reduced Fermi level and enhanced activation efficiency of Mg with suppressed segregation around the dislocations were demonstrated by Kelvin probe force microscopy and contact Hall measurements, respectively. A GaN p-channel metal oxide semiconductor device fabricated on the PSS displayed a twofold higher forward current density and superior gate controllability compared with that fabricated on a conventional sapphire substrate.

Toward Reduced Interface Contact Resistance: Controllable Surface Energy of Sb2Te3 Films via Tuning the Crystallization and Orientation.

The electrical contact resistance between a metal and semiconductor is one of the keys to improving the output performance of thin-film thermoelectric devices. Herein, we reduced the interface contact resistance by controlling the surface energy of a Sb2Te3 semiconductor via tuning of the crystallization and orientation, preparing an intrinsically compact and flat Sb2Te3 film with high surface energy and low roughness, which can give rise to a low average specific contact resistivity (8.2 × 10-6 Ω cm2) with a Ni/Cu metal. The improvement in interface electrical properties is due to the increase in the surface energy and decrease in the surface roughness of the semiconductor surface, which lead to a transformation from three-dimensional island-shaped nucleation to two-dimensional layered nucleation for surface-attached metal films, forming a longitudinally tight connection contact with a low resistance. This approach allows the resistivity to become close to the fundamental theoretically calculated limit. Our work provides a new idea for reducing the contact resistivity of thin-film thermoelectric devices, which is conducive to supporting the development of thermoelectric semiconductor planarization.

Improvement of Fermi-Level Pinning and Contact Resistivity in Ti/Ge Contact Using Carbon Implantation.

Effects of carbon implantation (C-imp) on the contact characteristics of Ti/Ge contact were investigated. The C-imp into Ti/Ge system was developed to reduce severe Fermi-level pinning (FLP) and to improve the thermal stability of Ti/Ge contact. The current density (J)-voltage (V) characteristics showed that the rectifying behavior of Ti/Ge contact into an Ohmic-like behavior with C-imp. The lowering of Schottky barrier height (SBH) indicated that the C-imp could mitigate FLP. In addition, it allows a lower specific contact resistivity (ρc) at the rapid thermal annealing (RTA) temperatures in a range of 450–600 °C. A secondary ion mass spectrometry (SIMS) showed that C-imp facilitates the dopant segregation at the interface. In addition, transmission electron microscopy (TEM) and electron energy loss spectroscopy (EELS) mapping showed that after RTA at 600 °C, C-imp enhances the diffusion of Ge atoms into Ti layer at the interface of Ti/Ge. Thus, carbon implantation into Ge substrate can effectively reduce FLP and improve contact characteristics.

A prototype thermoelectric module based on p-type colusite together with n-type nanostructured PbTe for power generation

Thermoelectric power generation from the prototype π-shaped module composed of p-type colusite (Cu26Cr2Ge6S32) and n-type nanostructured PbTe (Pb0.98Ga0.02Te-3% GeTe) was demonstrated in this study. The thermoelectric figure of merit zT of Cu26Cr2Ge6S32 and Pb0.98Ga0.02Te-3% GeTe was ∼0.8 and ∼1.2 at 665 K, respectively. In PbTe, transmission electron microscopic images and energy-dispersive x-ray elemental maps reveal the insertion of nanoscale precipitates induced by the GeTe alloying. Contact layers based on Au and Co-Fe were used for p- and n-type thermoelectric legs, respectively, which allow the low electrical specific contact resistances of ≤10 × 10−10 Ω m2 at room temperature. Maximum thermoelectric conversion efficiency ηmax of ∼5.5% was obtained for the Cu26Cr2Ge6S32 and Pb0.98Ga0.02Te-3% GeTe-based two-pair module when the hot-side Th and cold-side Tc temperatures were maintained at 673 and 283 K, respectively. A three-dimensional finite-element simulation predicts the ηmax of ∼7.1% for the module at Th and Tc of 673 and 283 K, respectively.

A general design strategy for thermoelectric interface materials in n-type Mg3Sb1.5Bi0.5 single leg used in TEGs

The reliability of thermoelectric power generators (TEGs) depends heavily on the contact interface between thermoelectric (TE) materials and electrodes. We propose a general alloying approach for generating TE interface materials (TEiMs) for n-type Mg3Sb1.5Bi0.5 systems. The TEiM serves as a metallisation layer or barrier that precedes the soldering assembly. We first selected Fe from 15 elements as the matrix element considering the criteria of high bonding strength and low interfacial resistivity. Following the principles of high bonding propensity, coefficient of thermal expansion (CTE) matching, diffusion passivation, and dopant inactivation, two types of ternary alloys (Fe7Mg2Cr and Fe7Mg2Ti) with shear strengths (σs) of > 40 MPa and the specific contact resistivities (ρc) of < 5 µΩ cm2 were obtained. Furthermore, the thermal stability of the TEiM/Mg3Sb1.5Bi0.5 contact interface was investigated employing aging treatment. The contact interface exhibited high shear strength (σs>30MPa), low specific contact resistivity (ρc<10μΩcm2), and excellent thermal stability after aging treatment at 400 °C for 15 days. The general TEiM design strategy presented herein will contribute to further optimization of contact interfaces in TEG devices.

Investigation of Ni/Al/Ti Ohmic Contact on N-Type 4H-SiC

In order to understand the contribution of various metals in the formation of ohmic contacts, Ni/Al/Ti ohmic contacts on n-type 4H-SiC in terms of a different annealing temperature and Ti composition are investigated, which is more difficult to form than p-type ohmic contact. The formation of the Ni/Al/Ti metal alloy system is much more sensitive to metal composition than annealing conditions. With the increase of metal composition, the contact with a high Ti content yields a lower specific contact resistivity compared with the low Ti contact. The annealed surface morphology and phase resultants were examined by scanning electron microscopy (SEM) and atomic force microscope (AFM), respectively. With the increase of Ti components, the surface morphology of the samples becomes more uniform and smoother, while the surface roughness remains unchanged. It implies that Ti metal can not only reduce the ohmic resistance, but also protect the surface of the sample and maintain the roughness.

Stacked-Interconnect for Monolithic Integration of Low-Temperature Polysilicon and Amorphous Metal-Oxide Thin-Film Transistors

While offering a range of practical benefits, the monolithic integration of low-temperature polysilicon (LTPS) and amorphous metal-oxide thin-film transistors presents several incompatibility issues regarding materials and processes. Presently addressed are two critical ones arising from the back-end processes of contact treatment and metallization. Both are resolved by employing a stacked-interconnect consisting of two conductor layers, with each layer forming the preferred contact electrodes for one of the two types of transistors. At the expense of a slight increase in process complexity, a narrow distribution of low specific contact resistance ( ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> Ω·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) for both types of transistors was obtained, thus giving rise to more consistent transistor characteristics. Inverters consisting of complementary top-gate LTPS pull-up and bottom-gate indium-gallium-zinc oxide pull-down transistors were demonstrated, exhibiting a gain of 40 V/V and a rail-to-rail full swing.

Highly Conductive Nanocrystalline Diamond Films and Electronic Metallization Scheme.

By using a methane and hydrogen process gas mixture in an appropriate hot-filament CVD process without further dopant, high electrical conductivity of over 100 S/cm has been achieved in nanocrystalline diamond films deposited on silicon single-crystalline substrates. Furthermore, it was found that an oxygen reactive-ion etching process (O-RIE) can improve the diamond film surface’s electron affinity, thus reducing the specific contact resistance. The reduction of the specific contact resistance by a factor of up to 16 was realized by the oxygen ion etching process, down to . We provide a qualitative explanation for the mechanism behind the contact resistance reduction in terms of the electron affinity of the diamond surface. With the aid of XPS, AFM, and surface wetting measurements, we confirmed that a higher surface electron affinity is responsible for the lower specific contact resistance of the oxygen-terminated nanocrystalline diamond films.

High field-effect performance and intrinsic scattering in the two-dimensional MoS2 semiconductors

The mobility of MoS2 nanosheets plays an important role in the application of nanoelectronics. The two-dimensional (2D) MoS2 semiconductors have been investigated while the reported mobility varies enormously. We adopt a standard four-terminal electrical measurement and eliminate any contact contributions. We fabricated several tens of field-effect transistors (FETs) with MoS2 nanosheets exfoliated from the same MoS2 bulk. The MoS2 FETs can be grouped into either high- or low-mobility devices according to their temperature behaviors of mobilities. With an RT mobility higher than ~ 25 or ~ 30 cm2V-1s−1, the MoS2 FETs exhibit an increasing mobility with decreasing temperature, implying phonon scattering in these high-mobility (HM) devices. The HM devices are accompanied with metallic states and their conductivities close to ~ 1 e2/h. A low specific contact resistivity of ~ 450 Ω·μm is observed in these HM devices. In contrast, the MoS2 FETs with an RT mobility lower than ~ 30 or ~ 35 cm2V-1s−1, categorized as low-mobility (LM) devices, reveal a decreasing mobility with decreasing temperature. These LM devices show an insulating state, carriers suffering from impurity scattering, and a high contact resistance. Their temperature dependent resistances are highly concordant with the 2D Mott’s variable range hopping. These observations corroborate a large variation of intrinsic disorders in MoS2 nanosheets.

Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration

The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( ≤ 50 μm) using fine-pitch ( ≤ 10 μm) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal-metal [copper-copper (Cu-Cu)] thermal compression bonding was developed. Using this process, sub-10- μm-pitch interconnects with a low specific contact resistance of ≤ 0.7 Ω·μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> 2</sup> and high shear force of 90 N for 4-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( ≤ 500 μm) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<; 20 ps), low energy per bit (≤0.03 pJ/b), and high data rates (up to 10 Gb/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4- 23× higher data bandwidth, 3- 65× lower latency, and 5- 40× lower energy per bit compared to existing integration schemes.

Low Resistance Ohmic Contact on ZnO Thin Film Revealed by Schottky Barrier Height

A high performance electronic device can be fabricated by achieving a high quality metal thin film Ohmic contact to intrinsic ZnO. In the present work, the low specific contact resistance Cr/Au metallization scheme deposited on n-type intrinsic 100 nm RF sputtered ZnO (Zinc oxide) thin film on SiO2/p-Si (100), an integrated circuit (IC) compatible substrate is utilized for the first time. Several metallization schemes were reported in the literature till date but not chromium to ZnO. Schottky Barrier height method was used to analyze the specific contact resistance which was obtained from the current-voltage characteristics. Thermionic emission carrier transport is considered at the interface for barrier height analysis. Low specific resistance was initiated in this work owing to the single-crystalline and smooth surface of the ZnO thin film revealed by X-Ray Diffraction (XRD) and Atomic Force Microscope (AFM) analysis. The simulation of the device structure was performed by using ATLAS software. The experimental result were finally compared with simulation results and were found to be in close agreement with each other.

Nanofabrication of graphene field-effect transistors by thermal scanning probe lithography

The development of a scalable and cost-effective nanofabrication method is of key importance for future advances in nanoelectronics. Thermal scanning probe lithography (t-SPL) is a growing nanopatterning method with potential for parallelization, offering unique capabilities that make it an attractive candidate for industrial nanomanufacturing. Here, we demonstrate the possibility to apply t-SPL for the fabrication of graphene devices. In particular, we use t-SPL to produce high performing graphene-based field effect transistors (FETs). The here described t-SPL process includes the fabrication of high-quality metal contacts, as well as patterning and etching of graphene to define the active region of the device. The electrical measurements on the t-SPL fabricated FETs indicate a symmetric conductance at the Dirac point and a low specific contact resistance without the use of any contact engineering strategy. The entire t-SPL nanofabrication process is performed without the need for masks, and in ambient conditions. Furthermore, thanks to the t-SPL in situ simultaneous patterning and imaging capability, no markers are required. These features substantially decrease fabrication time and cost.

The Significant Effect of Carbon and Oxygen Contaminants at Pd/p‐GaN Interface on Its Ohmic Contact Characteristics

A low‐resistance Ohmic contact of Pd/Pt/Au metallization scheme is formed on a p‐type GaN film grown by metal‐organic chemical vapor deposition (MOCVD). Two samples are prepared to explore the effect of contaminations at the metal and GaN interface on the properties of the Ohmic contact. One directly transfers the fresh GaN film from MOCVD to the metal deposition chamber through an ultrahigh vacuum (UHV) tube, without exposing the GaN surface to air; the other transfers the GaN film from MOCVD to metal deposition through the atmosphere. The results show a lower specific contact resistance (6.2 ± 0.9) × 10−5 Ω cm2 for the directly UHV‐transferred sample than the air‐transferred sample (2.1 ± 0.9) × 10−4 Ω cm2. Once exposed to air, carbonaceous particles and an amorphous oxide layer easily adhere to the p‐type GaN surface, which not only increase the Schottky barrier height but also generate more grain boundaries in the Pd/Pt/Au stacks. The grain boundaries, acting as diffusion channels, make Au atoms diffuse easily into the Pd layer and propagate to the p‐GaN surface layer after annealing. Therefore, the Ohmic contact fabricated in UHV ambience with lower oxygen and carbon contaminations at the interface shows superior characteristics than the samples prepared by the traditional method.