Low-resistivity Si Substrate Research Articles

Resistivity dependence on nanostructure formation in picosecond ablation of silicon and SERS-based sensing applications

We report on the influence of resistivity in picosecond (ps) laser ablation of silicon (Si) leading to the formation of diverse surface micro- and nanostructures. Subsequently, we investigated their potential in sensing applications based on the surface enhanced Raman scattering (SERS) technique. The varying resistivity (ρ 1: 1–10 Ω cm, ρ 2: 0.01–0.02 Ω cm, ρ 3: 0.001–0.005 Ω cm) Si wafers were subjected to cross patterned ps laser ablation in ambient air. Ladder-like microstructures embedded with numerous nano growths were formed on low resistivity Si (ρ 3) while similar micro- and nanostructures were observed on higher resistivity Si (ρ 2 < ρ 1). The structures were non-plasmonic and anti-reflecting in nature with an optical reflectance of <6% over a broad range of wavelengths (350–1200 nm). Non-plasmonic Si microstructures were subsequently transformed to plasmonic by means of deposition of a thin layer of gold (Au). Additionally, the effect of annealing on the evolution of nanostructures was also investigated. We employed these hybrid substrates for the trace detection of an explosive molecule, ammonium nitrate, and dye, malachite green. Our detailed SERS studies have demonstrated a superior enhancement in the trace detection of analytes for low resistivity Si substrate. However, the annealed hybrid substrates have demonstrated further improvement in the SERS signal (by at least one order of magnitude). These detailed SERS investigations provide us a proof of the sensitivity of different resistivity Si nano/microstructures.

GaN HEMTs on low resistivity Si substrates with thick buffer layers for RF signal amplification and power conversion

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices.

Fabrication of X-ray Gratings for Interferometric Imaging by Conformal Seedless Gold Electroplating.

We present a method to produce small pitch gratings for X-ray interferometric imaging applications, allowing the phase sensitivity to be increased and/or the length of the laboratory setup to be minimized. The method is based on fabrication of high aspect ratio silicon microstructures using deep reactive ion etching (Bosch technique) of dense grating arrays and followed by conformal electroplating of Au. We demonstrated that low resistivity Si substrates (<0.01 Ohm·cm) enable the metal seeding layer deposition step to be avoided, which is normally required to initiate the electroplating process. Etching conditions were optimized to realize Si recess structures with a slight bottom tapering, which ensured the void-free Au filling of the trenches. Vapor HF was used to remove the native oxide layer from the Si grating surface prior to electroplating in the cyanide-based Au electrolyte. Fabrication of Au gratings with pitch in the range 1.2–3.0 µm was successfully realized. A substantial improved aspect ratio of 45:1 for a pitch size of 1.2 µm was achieved with respect to the prior art on 4-inch wafer-based technology. The fabricated Au gratings were tested with X-ray interferometers in Talbot–Laue configuration with measured visibility of 13% at an X-ray design energy of 26 keV.

Average power handling capability on SiON thin film coplanar waveguide interconnections for MMICs

In this study, we investigated the average power handling capability (APHC) of silicon-oxy-nitride (SiON) thin-film-coated coplanar waveguide (CPW) interconnections for monolithic microwave integrated circuits (MMICs). SiON thin films were prepared through very-high-frequency plasma-enhanced chemical vapor deposition at 40.68 MHz. Films prepared under various annealing conditions were studied. The microwave characteristics of CPW interconnections were analyzed for fitting to the International Technology Roadmap for Semiconductors. SiON thin films were annealed under a vacuum condition for 60 s at 700 °C, 900 °C and 1100 °C. The use of coated and annealed SiON thin films on the low-resistivity Si substrate effectively improved the substrate resistivity, reduced microwave attenuation at 1100 °C, and enhanced the APHC of CPW interconnections. These results indicate that the proposed method is suitable for application to MMICs.

Wideband terahertz imaging pixel with a small on-chip antenna in 180 nm CMOS

We propose a Si-CMOS terahertz image sensor to resolve paucity of low-cost and small-size detectors. The imaging pixel consists of an on-chip antenna and an amplifier acting as envelope detector. The pixel uses a microstrip patch antenna for receiving THz waves. However, the antenna’s narrow bandwidth and large ground plane size causes major problems. A low-resistivity Si substrate degrades the gain of planar antennas besides the microstrip patch antenna. We introduce an on-chip folded-slot antenna to reduce the pixel size and prevent gain degradation due to the Si substrate. The antenna has a broader bandwidth and higher gain than conventional on-chip slot antenna. We fabricated the patch/folded-slot types of the pixel circuits by using 0.18 μm CMOS process. Measurement results show that the folded-slot antenna has a broader bandwidth from 850 GHz to 1.05 THz.

AlGaN/GaN High Electron Mobility Transistors with a p-GaN Backgate Structure

GaN based materials are widely used for power devices. AlGaN/GaN heterostructure is able to form high mobility 2DEG channel by its spontaneous and piezoelectric polarization at the AlGaN/GaN interface. Therefore, AlGaN/GaN HEMT is a promising candidate for next generation power device because of its high breakdown voltage, high current density and low on-state resistance (Ron). For efficient power switching applications, the E-mode operation with positive threshold voltage and low leakage current are required. Many efforts have been devoted to make AlGaN/GaN HEMT to achieve E-mode operation, such as gate recess, F-ion implements and p-GaN gate structures. In this study, a p-GaN backgate layer is applied to AlGaN/GaN HEMTs. Additional control ability under the channel layer is observed by applying bias at the p-GaN layer. The device can be turned off easily due to the p-GaN layer under channel layer, which depletes carriers in channel under suitable bias. Simulation and measurement results show the shift of threshold voltage toward positive for possible E-mode operation when backgate bias is negative. The simulation of AlGaN/GaN HEMT with a p-GaN backgate layer was performed with Silvaco TCAD tools including device structures, band diagrams, electron concentrations and ID-VG characteristic. A 30 nm p-GaN backgate layer was implemented under the 30-nm GaN channel with p-type doping of 2 ´ 1017 cm-3. The AlGaN/GaN HEMT epitaxial wafers on low-resistivity Si (111) substrates were grown by MOCVD. Device fabrication started with p-GaN activation in nitrogen atmosphere at 700°C for 15 minutes. Mesa isolation was etched by ICP down to the buffer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) and annealing at 875°C in a nitrogen atmosphere for 40 s. The contact to p-GaN layer was etched by ICP. Backgate metal was made by deposition of Ni/Au (20/20 nm) and annealing at 500°C in an oxygen atmosphere for 5 minutes. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metals were used to form front gate (FG). All the devices under test are with a gate-source distance of 4 μm, a gate length of 2 μm, and a gate-drain distance of 10 μm. The p-GaN backagte layer with bias is able to adjust the fermi levels in the quantum well thus the 2DEG concentration. Therefore, the threshold voltage shifts to positive values while applying negative backgate bias. Electrons are localized in the GaN channel layer when negative backgate bias was applied. This result is to justify the reduction of leakage current because leakage path through buffer layer is confined. From the simulated transfer characteristics of AlGaN/GaN HEMT with a p-GaN backgate under different backgate bias (VBG ). It is clearly to observe that the positive shift of threshold voltage (VTH) is due to the negative VBG . The simulated results showed the positive shift of VTH which was 5 V from VBG of 0 V to -14 V. Therefore, it possible to operate HEMT in either D-mode or E-mode operation by adjusting VBG . The measurement results showed the positive shift of VTH which was 0.55 V from VBG of 0 V to -14 V, with associated off-state leakage current reduction of 73.1%. However the shift of VTH is not as significant as in the simulation, the major reason is due to the bad p-GaN contact. The impact of p-GaN backgate structure in this study on the DC characteristics of AlGaN/GaN HEMTs was investigated. AlGaN/GaN HEMTs with a p-GaN backgate shows an additional control capability in 2DEG channel. Therefore, threshold voltage is adjustable and leakage current is improved by backgate bias. This extra gate control under channel layer is useful for circuit flexibility to achieve both D-mode and E-mode operations in the power device circuit design.

AlGaN/GaN HEMTs on Silicon With Hybrid Schottky–Ohmic Drain for RF Applications

In this paper, the AlGaN/GaN high electron mobility transistors on a low resistivity Si substrate with the hybrid drain structure for RF applications are analyzed in detail, based on measurements, TCAD simulation, model extraction, and delay time calculation of the transistors. Owing to the $E$ -field redistribution of the Schottky extension, both the leakage current and the breakdown voltage can be improved. Also, the enhanced RF performance can be attributed to the reduced transit time and increased transconductance, resulting from the increased electron velocity and reduced drain depletion width. With a 3- $\mu \text{m}$ extension length and a 0.2- $\mu \text{m}$ gate length, $f_{T}$ and $f_{\mathrm {MAX}}$ of transistors can be improved from 32.7 to 49.9 GHz (52.6%) and from 35.8 to 49.2 GHz (37.4%), respectively, with ON–OFF ratio enhancement by four orders of magnitude. The breakdown voltage was improved from 21 to 38 V (80.9%).

In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system**Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International

In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method.

Substrate-Coupled Cross-Talk Effects on an AlGaN/GaN-on-Si Smart Power IC Platform

Cross talks between low-voltage peripheral devices and high-voltage (HV) power devices on an AlGaN/GaN-on-Si smart power IC platform are investigated by monitoring the transfer, output, and transient characteristics of a low-voltage AlGaN/GaN high-electron mobility transistor (HEMT) with an HV bias stress applied to an adjacent isolated electrode. The electric measurement was conducted under two types of substrate termination, i.e., floating and grounded. The substrate termination is shown to be the critical factor in the cross talk. The low-voltage HEMT exhibits significant drain-current degradation with a floating substrate, but remains stable with a grounded substrate. It is determined that a coupling path of the switched HV stress is formed from the HV node to the floating low-resistivity Si substrate, and then from the substrate to the HEMT. The negative net charges in the GaN buffer are caused by the electrons injected from the 2DEG channel. It is found that a grounded substrate is helpful for eliminating the cross-talk effect.

Low Noise Amplifier With Integrated Balanced Antenna for 60 GHz Wireless Communications

The implementation of a dipole antenna co-designed and monolithically integrated with a low noise amplifier (LNA) on low resistivity Si substrate (20 Ω·cm) manufactured in 0.35 μm commercial SiGe HBT process with f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 170 GHz and 250 GHz is investigated theoretically and experimentally. An air gap is introduced between the chip and a reflective ground plane, leading to substantial improvements in efficiency and gain. Moreover, conjugate matching conditions between the antenna and the LNA are exploited, enhancing power transfer between without any additional matching circuit. A prototype is fabricated and tested to validate the performance. The measured 10-dB gain of the standalone LNA is centered at 58 GHz with a die size of 0.7 mm × 0.6 mm including all pads. The simulated results showed antenna directivity of 5.1 dBi with efficiency higher than 70%. After optimization, the co-designed LNA-Antenna chip with a die size of 3 mm × 2.8 mm was characterized in anechoic chamber environment. A maximum gain of higher than 12 dB was obtained.

High-Efficiency and High-Power Microwave Amplifier Using GaN-on-Si FET With Improved High-Temperature Operation Characteristics

We have successfully developed high-efficiency and high-power microwave amplifiers using a GaN field-effect transistor (FET) on a low-resistivity (LR) Si substrate for the first time. By introducing the LR Si substrate whose resistivity is less sensitive over temperature, the efficiency characteristics in high-temperature operation were significantly improved. In order to overcome the RF loss increase due to the utilization of the LR Si substrate, we have optimized the device structure of the FET by using an RC loss model accounting for drain-to-source capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> ) and substrate resistance. High-efficiency characteristics were realized by optimizing the buffer structure and electrode structure. Furthermore, we have investigated efficiency improvement by second harmonic termination. The developed single-ended amplifier realized the saturation output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 54 dBm, the linear gain (GL) of 19 dB, and the high efficiency of 33.5% at 8-dB back-off output power level under a WCDMA signal condition of 2.14 GHz at 50-V operation. The inverted Doherty amplifier using a pair of the 250-W GaN FETs delivered the P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> of 57.3 dBm with the GL of 15.5 dB under a pulsed continuous wave signal condition of 2.14 GHz, and demonstrated the digital pre-distortion linearization characteristics with the high efficiency of 48% and the adjacent channel leakage power ratio of -55 dBc at 50 dBm. These results are comparable to the best performance among the ever reported GaN on SiC FET high-power amplifiers.

Investigation of buffer traps in AlGaN/GaN-on-Si devices by thermally stimulated current spectroscopy and back-gating measurement

Thermally stimulated current (TSC) spectroscopy and high-voltage back-gating measurement are utilized to study GaN buffer traps specific to AlGaN/GaN lateral heterojunction structures grown on a low-resistivity Si substrate. Three dominating deep-level traps in GaN buffer with activation energies of ΔET1 ∼ 0.54 eV, ΔET2 ∼ 0.65 eV, and ΔET3 ∼ 0.75 eV are extracted from TSC spectroscopy in a vertical GaN-on-Si structure. High back-gate bias applied to the Si substrate could influence the drain current in an AlGaN/GaN-on-Si high-electron-mobility transistor in a way that cannot be explained with a simple field-effect model. By correlating the trap states identified in TSC with the back-gating measurement results, it is proposed that the ionization/deionization of both donor and acceptor traps are responsible for the generation of buffer space charges, which impose additional modulation to the 2DEG channel.

Resistivity changes of low resistivity Si substrates by rapid thermal processing and subsequent annealing

AbstractThe resistivity change of low resistivity Si substrates by rapid thermal processing (RTP) and subsequent low tem‐perature annealing is reported. The observed resistivity increase after RTP can be explained by dopant deactivation due to trapping by dopant atoms of intrinsic point defects created during the high temperature step. Similar dopant deactivation is observed during growth of low resistivity single crystals or epitaxial layers.The stability of the intrinsic point defect‐dopant clusters and the recovery of resistivity is studied by low temperature anneals ranging from 300 to 650 °C. Results are presented on As (3‐5 mΩcm), P (1‐2 mΩcm), (17‐18 mΩcm) and B (16‐17 mΩcm) doped Si substrates. The observations are explained on the basis of a continuum model for intrinsic point point defect trapping by dopants. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Empirical correlation for minority carrier lifetime to defect density profile in germanium on silicon grown by nanoscale interfacial engineering

High-quality Ge-on-Si heterostructures have been explored for many applications, including near infrared photodetectors and integration with III–V films for multijunction photovoltaics. However, the lattice mismatch between Ge and Si often leads to a high density of defects. Introducing annealing steps prior to and after full Ge island coalescence is found to reduce the defect density. The defect density in Ge is also found to decrease with increasing dopant density in Si substrates, likely due to the defect pinning near the Ge-Si interface by dopants. The authors establish an empirical correlation between the minority carrier lifetime (τG) and the defect density in the Ge film (ρD) as a function of distance from the Ge-Si interface: τGe = C/ρD, where C is a proportionality constant and a fitting parameter which is determined to be 0.17 and 0.22 s/cm2 for Ge films grown on low-doped, high-resistivity Si substrates and high-doped, low-resistivity Si substrates, respectively. The effective minority carrier lifetime measured as a function of Ge film thickness is then related to the recombination velocity on Ge film surface, average minority carrier lifetime within Ge film, and recombination velocity at the Ge-Si interface. Using this relation, the authors estimate the Ge-Si interface recombination velocity for Ge films grown on low-doped, high-resistivity and high-doped, low-resistivity Si substrates to be 220 and 100 cm/s, respectively.

Opto-chemical sensor system for the detection of H2 and hydrocarbons based on InGaN/GaN nanowires

We report on an all-optical sensor system that employs InGaN/GaN nanowires (NWs) as opto-chemical transducers. The NWs, grown by plasma-assisted molecular beam epitaxy on low-resistivity n-type Si (1 1 1) substrates, exhibit an efficient room-temperature photoluminescence (PL) that persists up to about 200 °C. After deposition of a thin (5 nm) catalytic Pt-film onto the NWs the PL intensity rises when the NWs are exposed to small concentrations of hydrogen and hydrocarbons. The gas response of the NWs was analyzed using an integrated sensor system with fiber-coupled excitation from a GaN-based power LED emitting at 365 nm and a fiber coupled photo multiplier tube for detection. With this setup, H2 concentrations as low as 200 ppb and C2H2 concentrations as low as 5 ppm could be detected when the transducers were operated at temperatures around 80 °C. This opto-chemical transducer principle is best suited for safety-critical applications where a reliable media separation is required.

High-Gain Silicon On-Chip Antenna With Artificial Dielectric Layer

On-chip antennas are demanded to further lower the cost of wireless CMOS ICs. The low resistivity of silicon substrates is a major obstacle to fabricate high-gain on-chip antennas. We placed an artificial dielectric layer (ADL) between an antenna and Si substrate to improve the antenna gain. A half-wave dipole-antenna that has ADL was designed and fabricated using a CMOS-compatible process with one poly-Si and two metal layers. Using the ADL enhanced gain by 3-dB. The measured gain was the highest ever achieved for the antennas operating at around 10 GHz on low-resistivity Si substrates. A method for further improvement is discussed.

Novel low-temperature variable inductors using porous anodic alumina

In this study, the authors study the benefits of using porous anodic alumina (PAA) as a new material to develop tunable RF micro-electro-mechanical systems (MEMS) inductors. To the authors knowledge, this is the first time that PAA material is proposed and successfully used as a structural material for MEMS devices and for fabrication of tunable inductors. The authors explain the fabrication process for producing tri- and bi-layer of PAA/aluminium or PAA/gold. These structures are used as thermal actuators to provide tunability for the inductor. The PAA layer is fabricated using an inexpensive simple procedure at a low-temperature process of 80°C. The experimental results for a tri-layer of Al-PAA-Al inductor exhibits a measured wide tuning range of 31% with inductor variation of 6.5-8.5 nH at 3 GHz and a quality factor of 6 on low-resistivity Si substrate. To improve the quality factor, bimorph layers of gold and PAA are fabricated on alumina substrates. The quality factor has greatly improved. A peak quality factor of over 20 with a tuning range of 18% is demonstrated.

Room temperature electroluminescence from ZnO/Si heterojunction devices grown by metal–organic chemical vapor deposition

Heterojunction light-emitting diodes with ZnO/Si structure were fabricated on both high-resistivity (p) and low-resistivity (p +) Si substrates by metal–organic chemical vapor deposition technology. Fairly good rectifications were observed from the current–voltage curves of both heterojunctions. Ultraviolet (UV) and blue-white electroluminescence (EL) from ZnO layer were observed only from ZnO/p +-Si heterojunction under forward bias at room temperature (RT), while strong infrared (IR) EL emissions from Si substrates were detected from both ZnO/p-Si and ZnO/p +-Si heterojunctions. The UV and IR EL mechanisms have been explained by energy band structures. The realization of RT EL in UV–visible and IR region on Si substrate has great applicable potential for Si-based optoelectronic integrated circuits.

High-Q micromachined three-dimensional integrated inductors for high-frequency applications

Three-dimensional micromachined inductors are fabricated on high-resistivity (10kΩcm) and low-resistivity (10Ωcm) Si substrates using a stressed metal technology. On high-resistivity Si substrate with low-k dielectric material (SU-8™), this technology achieves a quality factor Q of 75 for a 1nH inductor at frequencies around 4GHz and a self-resonant frequency fsr above 20GHz. Using Si bulk micromachining to etch away the low-resistivity Si substrate with a combination of deep reactive ion etching and tetramethyl ammonium hydroxide etching methods, a 1.2nH inductor achieves a peak quality factor Q of 140 at a frequency of 12GHz with a self-resonant frequency fsr above 40GHz. The dependence of high-frequency performance on the inductor’s variables, such as the number of turns, turn-to-turn gap, and substrate type, has been investigated. Excellent performance is achieved by removing the substrate due to the complete elimination of substrate losses and the reduction of the parasitic capacitance. This technology is simple and provides high performance integrated inductors on Si or compound-semiconductor platforms.

Design of high-Q 3-D integrated inductors for high frequency applications

Design of 3-Dimensional micromachined inductors on high-(10 K ·cm) and low-resistivity(10 ·cm) Si substrate fabricated using stress metal technology we have developed [1, 2] is presented. Using hig...