Low-resistivity Si Substrate Research Articles

Micromachined DC contact capacitive switch on low-resistivity silicon substrate

A DC contact capacitive shunt switch on low-resistivity Si substrate is designed and demonstrated. There are two main differences between this design and the conventional capacitive shunt switch. First, the dielectric layer is fabricated on the ground planes of the coplanar waveguide (CPW) transmission line. The contact between the metal bridge and the center conductor becomes DC contact when the metal bridge is driven down. As a result, the down-state capacitance degradation problem can be solved and the down-state capacitance as high as 30pF can be achieved. Second, the switch is fabricated on a low-resistivity silicon substrate. This is the first time where a RF MEMS switch can be fabricated on a low-resistivity silicon substrate without any wafer transfer technology; thus, it can greatly simplify the fabrication process and reduce cost. Measurement results show that the insertion loss is lower than 0.4dB until 26.5GHz and the isolation is 15dB at 1GHz, 26dB at 10GHz and 27dB at 26.5GHz. The down-state resistance and the inductance are 1.3Ω and 2 pH, respectively.

Structural Properties of Ultrathin Amorphous Silicon Oxynitride Layers

7-nm-thick amorphous silicon oxynitride (a-SiOxNy) layers were prepared at 300°C using a plasma nitridation technique on different types of crystalline Si substrates and under different ammonia flow rates, [NH3]. The compositional and structural properties of the a-SiOxNy layers were examined using current–voltage (I–V), capacitance–voltage (C–V), electron spin resonance (ESR), Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared (FT-IR) measurements. A strong correlation between the changes in the I–V, C–V characteristics and in the ESR spin density (Ns) was obtained. The use of low-resistivity Si substrates enabled us to assess simultaneously the changes in the defect density and the electrical properties. Based on the FT-IR results, the changes in the 800 and 1070 cm-1 absorption bands are discussed in connection with the structural change.

Microwave properties of SrTiO3/SrRuO3/CeO2/YSZ heterostructure on low-resistivity silicon

Abstract Properties of thin film SrTiO 3 /SrRuO 3 /CeO 2 /YSZ heterostructures on low-resistivity (25 Ωcm) Si substrates are studied at microwave frequencies. Heterostructures are grown by laser ablation at different conditions and characterized by XRD. Coplanar capacitors with 2 μm gap are formed by a lift-off process of the Au/Ti electrodes deposited by e-beam evaporation on the surface of heterostructures. Microwave properties of the capacitors are measured at room temperature in the range of 1–50 GHz as a function of electric field. The measured tunability of the capacitors is in the range of 10–20%. The loss in capacitors is caused mainly by the Si substrate with maximum value around the dielectric relaxation frequency 6 GHz. The intrinsic loss tangent (0.08 at 50 GHz) of capacitors is calculated from equivalent circuit model by removing the substrate loss.

Low-loss CPW on low-resistivity Si substrates with a micromachined polyimide interface layer for RFIC interconnects

The measured and calculated propagation constant of coplanar waveguide (CPW) on low-resistivity silicon (1 /spl Omega//spl middot/cm) with a micromachined polyimide interface layer is presented in this paper. With this new structure, the attenuation (decibels per centimeter) of narrow CPW lines on low-resistivity silicon is comparable to the attenuation of narrow CPW lines on high-resistivity silicon. To achieve these results, a 20-/spl mu/m-thick polyimide interface layer is used between the CPW and the Si substrate with the polyimide etched from the CPW slots. Only a single thin-film metal layer is used in this paper, but the technology supports multiple thick metal layers that will further lower the attenuation. These new micromachined CPW lines have a measured effective permittivity of 1.3. Design rules are presented from measured characteristics and finite-element method analysis to estimate the required polyimide thickness for a given CPW geometry.

Improved microwave performance on low-resistivity Si substrates by Si/sup +/ ion implantation

Microwave characteristics of spiral inductors on low-resistivity Si substrates have been improved by implanting Si/sub 28//sup +/ ions. Spiral inductors fabricated on these implanted substrates demonstrate better Q-value and microwave performance. The Q-value of inductor enhanced 60% on the implanted substrates than that of low resistivity Si substrates. An equivalent circuit model of inductor has been evaluated to discuss the effect of substrate loss.

Three-dimensional silicon MMIC's operating up to K-band

This paper presents three-dimensional (3-D) Si monolithic microwave integrated circuit (MMIC) technology and Si MMIC operation up to K-band using this technology, and describes X- and K-band mixers with design details and measurements. The 3-D Si MMIC technology isolates passive circuits from the low-resistivity Si substrate. The evaluations use Si bipolar transistors with an emitter size of 0.3 /spl mu/m/spl times/13.4 /spl mu/m/spl times/9 and f/sub max/ of 30 GHz. The mixers are base and collector LO injection types. The mixers, fabricated in an area of 0.76 mm/spl times/0.54 mm for the X-band mixers and in 0.46 mm/spl times/0.42 mm for the K-band mixers, exhibit a frequency conversion loss of 5-12 dB from 3.5 to 10 GHz and from 10 to 25 GHz. This technology is extremely effective for single-chip integration of receivers and transmitters and also for mixed-mode MMIC's up to K-band frequencies.

L-band internally matched Si-MMIC front-end

A 1.9 GHz-band internally matched Si-MMIC front-end, fabricated in standard 0.8 /spl mu/m BiCMOS process, was developed. This IC front-end contains a MOSFET T/R switch, a two-stage BJT low noise amplifier (LNA), and a down converter BJT mixer. Since the circuits are monolithically integrated on a low resistivity Si substrate, the coplanar waveguide (CPW) type spiral inductors are used to reduce the dielectric loss of on-chip matching circuits. The T/R switch has measured insertion loss of 2.5 dB and isolation of 25.5 dB at 0/3 V control voltage. The two-stage LNA has gain of 17.1 dB and noise figure (NF) of 2.9 dB at 2 V, 4 mA dc supply. The mixer has conversion gain of 5.9 dB and NF of 15 dB at 2 V, 1.7 mA dc supply. The measured performance of the fabricated Si-MMIC front-end indicates the possibility of application to mobile communication handset terminals.