Low Quiescent Power Research Articles

Design of a Wide Input Voltage Low Quiescent Current LDO

A low-dropout linear regulator (LDO) with wide input voltage range, wide output voltage range and low quiescent current power consumption is proposed, which is applied to the switching power supply chip to power the internal module of the switching power supply chip. The low-dropout linear regulator is based on a P-type PowerFET design consisting of an error amplifier, a Bandgap reference. The circuit was designed and implemented by SMIC 0.18um BCD process, simulated and verified using Spectre software. The simulation results show that the linear regulation is 0.04mV/V in the input voltage range of 3.5-30V, and the load regulation is 1mV/mA in the output load current range of 10uA to 10mA, and the quiescent current is only 10uA.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control

This article presents a highly efficient buck converter with sub-nW quiescent power and wide dynamic range for ultra-low-power (ULP) Internet-of-Things (IoT) systems-on-chip (SoCs). To optimize the SoC power consumption and performance, this buck converter supports fast dynamic voltage and frequency scaling (DVFS) and fast load-transient response (FLTR) using an asynchronous control scheme. To achieve robust and high-efficiency power delivery over process, voltage, and temperature variations, an adaptive deadtime controller (ADTC) is proposed with minimized area and power overhead. The power stage and gate drivers are optimized by a length split technique and a strong-up weak-down (SuWd) scheme to achieve low quiescent power. In addition, the buck converter is fully self-contained with a bias generator (BG), clock, and power-on-reset (PoR) integrated on-chip. Fabricated in 65-nm CMOS, measurement results show that the buck converter achieves 802-pW quiescent power and 93% peak efficiency at 1.5-V input voltage. The measured dynamic range is from 0.5 to 2.75 mW, which is over six orders of magnitude. The measured voltage droop is 56 mV for a 45-nA-to-1-mA load current step and DVFS up- and down-tracking takes 10.57 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$19.81~\mu \text{s}$ </tex-math></inline-formula> for an 88- and 92-mV reference step, respectively. This sub-nW buck converter integrates fast DVFS and FLTR features with a wide dynamic range making it suitable for ULP IoT applications.

A cryogenic low power CMOS analog buffer at 4.2K

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.

A low quiescent power wireless rotating machinery condition monitoring system

Vibration-based monitoring of rotating machinery is rapidly evolving within the aerospace industry with priority on detecting impending failures. The workhorse of such monitoring system remains a piezoelectric-based accelerometers which requires a wired-harnesses, connectors, significant power, and signal conditioning, etc. Raytheon Technologies Research Center (RTRC) along with Collins Aerospace and Sandia National Laboratory have jointly developed an Aluminum-Nitride Resonant Integrated Accelerometer Sensors (ARISE). &#x0D; This is a low power alternate for a conventional wired vibration-based monitoring system. This self-contained sensor system includes: (1) a low quiescent power sensing element with a wake-up module, (2) a wireless communication module, and (3) a coin-cell battery. Leveraging work performed under Defense Advanced Research Projects Agency (DARPA) N-Zero program. This wireless health monitoring system can operate in a quiescent low power mode (~10nW) for a period of several years without servicing. With an exceedance above a preset vibration level (at designate characteristic frequencies), the sensor wakes up and wirelessly sends a warning of a precursor-to-failure.&#x0D; The ARISE sensor and wake-up module package has been validated with a replicated vibration environment acquired from a selected rotating machinery subject to progressive damage at the Structural Dynamics Laboratory at RTRC. The failure precursor is successfully detected by the sensor which triggers the wake-up module.&#x0D; This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) Micro Technology Office (MTO), under Aluminum-Nitride Resonant Integrated Accelerometer Sensors (ARISE) program.

A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz

High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 $\mu \text {s}$ and has a quiescent current of 5.6 $\mu \text {A}$ . For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.

A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power

A buck converter in 65-nm CMOS is optimized for a low quiescent power of 240 pW. It operates with input 1.2-3.3 V and regulates the output from 0.7-0.9 V. Control circuits are designed for low leakage and static current, and scale in power over a hertz to megahertz frequency range, resulting in a wide load current dynamic range of 2×0 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . With a 2-V input, the converter has a peak efficiency of 89% and delivers load currents of 500 pA to 1 mA with efficiency better than 50%. The peak efficiency is 92% for a 1.2-V input.

Low-power transcutaneous current stimulator for wearable applications

BackgroundPeripheral neuropathic desensitization associated with aging, diabetes, alcoholism and HIV/AIDS, affects tens of millions of people worldwide, and there is little or no treatment available to improve sensory function. Recent studies that apply imperceptible continuous vibration or electrical stimulation have shown promise in improving sensitivity in both diseased and healthy participants. This class of interventions only has an effect during application, necessitating the design of a wearable device for everyday use. We present a circuit that allows for a low-power, low-cost and small form factor implementation of a current stimulator for the continuous application of subthreshold currents.ResultsThis circuit acts as a voltage-to-current converter and has been tested to drive + 1 to − 1 mA into a 60 kOmega load from DC to 1 kHz. Driving a 60 kOmega load with a 2 mA peak-to-peak 1 kHz sinusoid, the circuit draws less than 21 mA from a 9 V source. The minimum operating current of the circuit is less than 12 mA. Voltage compliance is ± 60 V with just 1.02 mA drawn by the high voltage current drive circuitry. The circuit was implemented as a compact 46 mm × 21 mm two-layer PCB highlighting its potential for use in a body-worn device.ConclusionsNo design to the best of our knowledge presents comparably low quiescent power with such high voltage compliance. This makes the design uniquely appropriate for low-power transcutaneous current stimulation in wearable applications. Further development of driving and instrumentation circuitry is recommended.

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage

A programmable gain amplifier (PGA) is presented, targeting amplifying input signal with high dynamic range and low noise. The proposed PGA adopts fully balanced differential difference amplifier (FBDDA) as main amplifier. A class-AB implementation of output stage is advantageous in order to achieve high current driving capability with very low quiescent power consumption. Combining resistor-feedback loop controlled by digital signal, the proposed PGA achieves a dB-linear gain range from 0 to 15dB with a gain step of 1dB. Compared with previous works, the theoretical analysis and measurement results prove that the proposed structure has lower noise. The circuit was designed and fabricated in SMIC 0.18µm 3.3V process, showing a gain error of less than 0.25dB, a third harmonic distortion (HD3) of better than −83dB and a thermal noise of 1.6 nv/Hz. The measurement results indicate that the PGA described here has a −3dB bandwidth of 387.5MHz at maximum gain of 15dB. The PGA occupies a chip area of 0.1mm2.

A Performance-Aware Low-Quiescent Headphone Amplifier in 65-nm CMOS

A low-quiescent high-performance class-AB headphone amplifier is presented. The effect of the input-referred offset on the quiescent power of audio power amplifier (APA) that drives very small resistive load is described and analyzed. A digitally assisted offset calibration-based APA topology together with improved frequency compensation is proposed. This permits the use of low quiescent power and small compensation capacitance. Implemented in 65-nm CMOS technology, the amplifier occupies an area of 0.15 mm2 and consumes 0.4 mW at ±1 V supplies. At the load of 16 $\Omega $ //200 pF, the gain-bandwidth product is 1.78 MHz using a total compensation capacitance of 8.5 pF. Other performance metrics are measured with −89-dB total harmonic distortion (THD+N), 93.5-dB signal-to-noise ratio, 84-dB power supply rejection ratio (PSRR+), and 105-dB PSRR– @217 Hz. It can deliver a peak power of 35 mW (1.5 $V_{\mathrm{ pp}}$ swing) to the above load, yielding the best figure-of-merit (FOM) = (peak load power/quiescent power) and the best FOM2 = [peak load power/quiescent power $\ast $ (THD+N)%] with respect to other reported representative works.

A robust low quiescent current power receiver for inductive power transmission in bio implants

ABSTRACTIn this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.

(Invited) The Application of Advanced Sige Complementary Bipolar Technologies to High Speed and High-Precision Applications

SiGe has rapidly grown to a mature process technology addressing a broad array of applications. Most of the literature discussing these applications focuses on RF circuits and very high-speed data links; both take advantage of the high switching speed, low noise, and current handling capabilities afforded by SiGe transistors. The addition of germanium into a silicon bipolar junction transistor (BJT) technology allows the component engineer to optimize different parameters. These applications usually force the focus on Ft or Fmax. While these are also important in the design of precision circuits and or high linearity amplifiers, current gain (Hfe) and Early voltage (Va) are often design limitations that force use of more complex circuits. Additionally, usually only NPN transistors are available which can significantly complicate the design of critical analog building blocks. SiGe in fact provides significant performance boost to PNP transistors and in the last couple of decades complementary SiGe BJT processes are offered by several major semiconductor manufacturers. Although generally the focus has been on relatively low voltage devices with Bvceos of significantly less than 5V, SiGe can also be applied to the design of much higher voltage transistors with a significant boost in performance. Many integrated circuits are built in such complementary SiGe Bipolar technologies and offer significant advantages over equivalent devices built in more conventional processes. To address low voltage applications, we will discuss how complementary SiGe can be applied to the design of a high-speed 16bit analog to digital convertor (ADC) and the design of a special buffer amplifier developed to condition the signal fed to such ADCs. Higher voltage (+/-15V supplies) precision amplifiers are still a significant market and have warranted the development of specialized complementary SiGe technologies. We will work through the design of a typical amplifier and show how the improved transistors lead to better end-product performance. Feedback amplifiers are generally easier to stabilize if there are fewer gain stages. Compensation techniques are available to stabilize complex amplifier designs which generally sacrifice performance. The increased gain offered by SiGe BJTs compared to alternatives can reduce the number of gain stages needed to meet a specific specification. The availability of a complementary PNP transistor can also significantly simplify circuit design. The combination of the gain of the SiGe BJT (due to high Va and Hfe) together with the simplicity and symmetry offered by complementary bipolar circuit design enables the design of very high performance operational amplifiers. We will detail an ampliier designed for very high performance portable audio applications. The combination of high Early Voltage and high Beta allows for a simple, single gain stage implementation, which results in low quiescent power, high capacitive load drive and high PSRR. The high beta and Ft of the SiGe transistors make this performance possible at low quiescent power.

Design of a High Linearity 6-GHz Class-F Radio Frequency Power Amplifier

In this study, a high linearity class-F RF power amplifier is introduced. It is designed to operate at a frequency of 6 GHz with a bandwidth of 400MHz. The amplifier mixes between the characteristics of conventional switch mode class-F and class B amplifiers. It is biased at very low quiescent power, thus it dissipates negligible DC power in the absence of RF excitation. This makes it suitable for handset applications. The amplifier is designed and tested on Microwave Office Environments. It showed linear input/output characteristics for an input RF power range of -20 to 5d Bm. The amplifier collector efficiency is 80%, which is greater than that of ideal class-B power amplifier. In addition, it is sensitive to amplify low level RF signals, therefore it needs no preamplifier.

A 60%-Efficiency 20nW-500µW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for IoT Systems.

As Internet-of-Things (IoT) systems proliferate, there is a greater demand for small and efficient power management units. Fully integrated switched-capacitor (SC) DC-DC converters are promising candidates due to their small form factor and low quiescent power, aided by dynamic activity scaling [1–3]. However, they offer a limited number of conversion ratios, making them challenging to use in actual systems since they often require multiple output voltages (to reduce power consumption) and use various input power sources (to maximize flexibility). In addition, maintaining both high efficiency and fast load response is difficult at low output current levels, which is critical for IoT devices as they often target low standby power to preserve battery charge. This paper presents a fully integrated power management system that converts an input voltage within a 0.9-to-4V range to 3 fixed output voltages: 0.6V, 1.2V, and 3.3V. A 7-stage binary-reconfigurable DC-DC converter [1–2] enables the wide input voltage range. Three-way dynamic frequency control maintains converter operation at near-optimum conversion efficiency under widely varying load conditions from 5nW to 500µW. A proposed load-proportional bias scheme helps maintain high efficiency at low output power, fast response time at high output power and retains stability across the entire operating range. Analog drop detectors improve load response time even at low output power, allowing the converter to avoid the need for external sleep/wakeup control signals. Within a range of 1-to-4V input voltage and 20nW–500µW output power, the converter shows >60% conversion efficiency, while maintaining responsiveness to a 100× sudden current increase.

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18μm CMOS process to test the topology with a prototype global interconnect having a length of 10mm. Power consumption of the transceiver for a data rate of 2.5Gbps data is 2mW. This gives an energy efficiency of 0.8pJ/b.

Low power field generation for magneto-optic fiber-based interferometric switches

A new fiber-based, magneto-optic switch is proposed with a novel approach for low power and efficient operation. The switch, with reasonable switching speed compared to competitive designs, operates at considerably reduced power levels, which makes it a practical deployable solution. The basic switch setup consists of a Faraday rotator in a Sagnac fiber-optic interferometer in which optical switching is controlled by an electronic driving circuit. The electronic system generates a magnetic field through the Faraday rotator by driving current through a specially designed two-coil system. The new coil system allows for sufficient field generation at low quiescent power levels while maintaining very short optical rise and fall times. The design and considerations as well as the effect of mutual inductance between the two coils and its influence on switching times are investigated. The optical system consists of a Sagnac interferometer with a Faraday rotator within the Sagnac loop. Appropriate phase shift for interference is achieved by the proposed field generating system designed for the magneto-optical element. The theory of operation, design, experimental results, and optical and electronic setup are presented and analyzed.

Micropower high current‐drive class AB CMOS current‐feedback operational amplifier

AbstractA novel CMOS current‐feedback operational amplifier (CFOA) aimed to low‐power applications is proposed. The use of a compact class AB implementation allows high current‐drive capability and simultaneously very low quiescent power consumption. Measurement results of a fabricated prototype show for an inverting configuration a closed‐loop bandwidth of 1 MHz independent of gain setting, and a slew rate of 2V/µs for a load capacitance of 30 pF and a quiescent power consumption of 264µW. Copyright © 2010 John Wiley &amp; Sons, Ltd.

A Low Quiescent Biased Regulator With High PSR Dedicated to Micropower Sensor Circuits

A new micropower high power-supply-rejection (PSR) regulator, on the basis of op-amp-less architectural design, is presented in this paper. The proposed regulator is based on the embodiment of the Brokaw bandgap regulator circuit in an additional feedback control loop so as to achieve high efficiency in terms of referenced PSR bandwidth per current. The measured PSR performance without any filtering capacitor for a 50-kΩ nominal resistive load at 1 kHz and 1 MHz are obtained as -76 and -43 dB, respectively. The regulator, making use of native driving devices to improve the headroom, supports the supply range from 2 to 3.3 V. The output voltage is close to 1.8 V, having an untrimmed temperature coefficient of 117 ppm/°C from - 40°C to 125°C while drawing the quiescent current of only 5.65 μA. The regulator occupies an area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using current source model 1.8 V/3.3 V CMOS 0.18 μm triple-well process technology. The circuit is verified using the realistic BSIM3 models for simulation. Finally, the performance comparison with respect to the measured results of reported works, using technology normalized figure of merit, has validated that the proposed circuit technique offers good PSR results while having the advantages of low quiescent power, small size, and full integration without any off-chip capacitor. The proposed regulator is particularly suitable for micropower sensor circuits.

Low-Power High-Efficiency Class D Audio Power Amplifiers

The architecture, design, and implementation of two clock-free analog class D audio power amplifiers using 0.5 ¿m CMOS standard technology are introduced. The amplifiers are designed to consume significantly less power than former implementations. Both designs operate with a 2.7 V single voltage supply and deliver a maximum output power of 250 mW into an 8 ¿ speaker. The two class-D amplifiers are based on a hysteretic sliding mode controller, which avoids the complex task of generating the highly linear triangle carrier signal used in conventional architectures. The first design generates a two-level modulated signal, known as binary modulated amplifier (BMA); the second topology implements a three-level modulated signal, also called ternary modulated amplifier (TMA). The architectures and implementations are simple and compact, providing very low quiescent power consumption. Experimental results of the BMA/TMA yield an efficiency of 89/90% and a total harmonic distortion plus noise (THD+N) of 0.02/0.03%, respectively. The efficiency and linearity is comparable to state-of-the-art amplifiers but the static power consumption is less than one tenth of previous proposed architectures. Both class D amplifiers achieve a power supply rejection ratio greater than 75 dB at 217 Hz, and a signal-to-noise ratio (SNR) higher than 90 dB within the whole audio band. Each amplifier occupies less than 1.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.