Low-pressure Chemical Vapor Deposition Silicon Research Articles

Optical bandgap engineering in nonlinear silicon nitride waveguides.

Silicon nitride is a well-established material for photonic devices and integrated circuits. It displays a broad transparency window spanning from the visible to the mid-IR and waveguides can be manufactured with low losses. An absence of nonlinear multi-photon absorption in the erbium lightwave communications band has enabled various nonlinear optic applications in the past decade. Silicon nitride is a dielectric material whose optical and mechanical properties strongly depend on the deposition conditions. In particular, the optical bandgap can be modified with the gas flow ratio during low-pressure chemical vapor deposition (LPCVD). Here we show that this parameter can be controlled in a highly reproducible manner, providing an approach to synthesize the nonlinear Kerr coefficient of the material. This holistic empirical study provides relevant guidelines to optimize the properties of LPCVD silicon nitride waveguides for nonlinear optics applications that rely on the Kerr effect.

27 pT Silicon Nitride MEMS Magnetometer for Brain Imaging

We report the design, fabrication, and characterization of an ultrasensitive resonant (~300–400 Hz) magnetometer with 0.67-mV/nT sensitivity. The sensor was composed of a low stress (−14 MPa) low-pressure chemical vapor deposition silicon nitride cross bridge and a neodymium magnet. External magnetic field biasing (to modify the effective Hooke’s constant), shielding, mechanical isolation, and parametric amplification and feedback were used to progressively improve the sensor performance from 1 $\mu \text{T}$ minimum detectable signal to 27 pT; an improvement of five orders of magnitude. The sensor’s average temperature sensitivity around the room temperature was 11.9 pV/pT/°C.

Improving stress stability in low-pressure chemical vapor deposited silicon dioxide films by ion implantation

The stress state of low-pressure chemical vapor deposition (LPCVD) silicon dioxide (SiO2) films fluctuates upon aging due to the ambient moisture. The related variation of the SiO2 films is a key factor of device reliability. In this study, ion implantation is introduced to improve film stress stability. The stress state modified by ion implantation is discussed in detail and an analytical model is presented. The evolution of the stress in as-deposited and P+-, As+-, and B+-implanted LPCVD SiO2 films upon aging is investigated, and the bonding nature of the films is also studied to provide insight into the physical mechanisms involved. It is demonstrated that low implantation energy slightly modifies the stress in films. In addition, P+ ion is the most appropriate impurity ion to improve film stress stability, and the stress in P+-implanted LPCVD SiO2 film can be stabilized with a low tensile stress of 67MPa when the film is implanted at 15keV with a dose of 1×1015cm−2.

Normally Off AlGaN/GaN MIS-High-Electron Mobility Transistors Fabricated by Using Low Pressure Chemical Vapor Deposition Si<sub>3</sub>N<sub>4</sub> Gate Dielectric and Standard Fluorine Ion Implantation

This letter presents a fabrication technology of enhancement-mode (E-mode) AlGaN/GaN metal-insulator–semiconductor high-electron mobility transistors (MIS-HEMTs) using 10 keV fluorine ion implantation. An 8 nm low-pressure chemical vapor deposition silicon nitride layer was deposited on the AlGaN as gate dielectric and energy-absorbing layer that slows down the high energy (10 keV) fluorine ions to reduce the implantation damage. The E-mode MIS-HEMTs exhibit a threshold voltage as high as +3.3 V with a maximum drain current over 200 mA/mm (250 mA/mm for depletion-mode MIS-HEMTs) and a high on/off current ratio of $10^{9}$ . Meanwhile, the E-mode MIS-HEMT dynamic $R_{\mathrm{\scriptscriptstyle ON}}$ is only 1.53 times larger than the static $R_{\mathrm{\scriptscriptstyle ON}}$ after off-state $V_{\mathrm {DS}}$ stress of 500 V.

Synthesis and Characterization of LPCVD Polysilicon and Silicon Nitride Thin Films for MEMS Applications

Inherent residual stresses during material deposition can have profound effects on the functionality and reliability of fabricated MEMS devices. Residual stress often causes device failure due to curling, buckling, or fracture. Typically, the material properties of thin films used in surface micromachining are not very well controlled during deposition. The residual stress, for example, tends to vary significantly for different deposition conditions; experiments were carried out to study the polysilicon and silicon nitride deposited by Low Pressure Chemical Vapor Deposition (LPCVD) method at wide range of process conditions. High temperature annealing effects on stress in case polysilicon are also reported. The reduced residual stress levels can significantly improve device performance, reliability, and yield as MEMS devices become smaller.

Characterization of LPCVD amorphous silicon carbide (a-SiC) as material for electron transparent windows

We investigate on the physical and chemical properties of non-stoichiometric amorphous silicon carbide (a-SiCx) thin layers deposited by low-pressure chemical vapor deposition (LPCVD). Characterizations are specifically tailored to understand the suitability of a-SiCx as electron transparent window material. The structure, composition, continuity, intrinsic stress, etch-rates and roughness of the layers are determined. The a-SiCx layers are highly uniform and continuous, showing tensile intrinsic stress and high chemical inertness. The layer with the lowest roughness (0.22 nm) and intrinsic stress (0.7 GPa) is employed to fabricate electron transparent windows of 16 nm for use in a Transmission Electron Microscope (TEM). The resulting windows are highly transparent, enabling the acquisition of TEM images down to the resolution limit of the microscope (0.12 nm). Moreover, the a-SiCx windows show a resistance to electron beam damage which is up to 9 times higher than that of the commonly employed low-stress LPCVD silicon nitride (SiNx). Therefore, the proposed a-SiCx is particularly suited for TEM experiments where high chemical inertness and/or long exposures to the TEM electron beam are required. In addition, the a-SiCx layer could advantageously be employed in the design of microelectromechanical systems (MEMS), especially those operating in harsh environments.

Illumination effects on electrical characteristics of GaN/AlGaN/GaN heterostructures and heterostructure field effect transistors and their elimination by proper surface passivation

The effect of ambient illumination is investigated for differently processed GaN/AlGaN/GaN heterostructure materials. For samples of the same material with different passivation, the difference in sheet resistance of illuminated and non-illuminated material can be as large as 130% (for annealed heterostructure without passivation) and as small as 3% (for heterostructure passivated with low pressure chemical vapor deposition (LPCVD) silicon nitride). The time constant for the decay of the persistent photoconductance (PPC) is also very different for the differently processed samples. The majority of the effect on the conductance is from photons with energies between 3.1 and 3.7 eV. The investigation indicates that delayed recombination of electrons emitted from surface states and from deep level states in the AlGaN layer dominates the PPC. A theory is formulated by which the difference in illumination sensitivity for the differently passivated materials can be explained by different distributions of electrons between the channel two dimensional electron gas and an accumulation layer formed in the cap layer. For practical heterostructure field effect transistor (HFET) measurements, the illumination sensitivity is generally lower than that of the Hall measurements. Furthermore, HFETs fabricated with the LPCVD silicon nitride passivation are practically illumination invariant.

Metal-oxide-semiconductor field effect transistor humidity sensor using surface conductance

This letter presents a metal-oxide-semiconductor field effect transistor based humidity sensor which does not use any specific materials to sense the relative humidity. We simply make use of the low pressure chemical vapor deposited (LPCVD) silicon dioxide’s surface conductance change. When the gate is biased and then floated, the electrical charge in the gate is dissipated through the LPCVD silicon dioxide’s surface to the surrounding ground with a time constant depending on the surface conductance which, in turn, varies with humidity. With this method, extremely high sensitivity was achieved—the charge dissipation speed increased thousand times as the relative humidity increased.

Fracture toughness of silicon nitride thin films of different thicknesses as measured by bulge tests

A bulge test setup was used to determine the fracture toughness of amorphous low-pressure chemical vapor deposited (LPCVD) silicon nitride films with various thicknesses in the range 40–108nm. A crack-like slit was milled in the center of each free-standing film with a focused ion beam, and the membrane was deformed in the bulge test until failure occurred. The fracture toughness KIC was calculated from the pre-crack length and the stress at failure. It is shown that the membrane is in a transition state between pure plane-stress and plane-strain which, however, had a negligible influence on the measurement of the fracture toughness, because of the high brittleness of silicon nitride and its low Young’s modulus over yield strength ratio. The fracture toughness KIC was found to be constant at 6.3±0.4MPam1/2 over the whole thickness range studied, which compares well with bulk values. This means that the fracture toughness, like the Young’s modulus, is a size-independent quantity for LPCVD silicon nitride. This presumably holds true for all amorphous brittle ceramic materials.

Influences of deposition and crystallization kinetics on the properties of silicon films deposited by low-pressure chemical vapour deposition from silane and disilane

The paper deals with the properties of silicon films obtained by low-pressure chemical vapour deposition (LPCVD). Two gaseous sources characterized by different deposition temperatures, i.e. disilane Si 2H 6 (420–520 °C) and silane SiH 4 (520–750 °C), was studied in order to understand the influences of deposition and crystallization kinetics on silicon film properties. Thus, the deposition of amorphous, semi-crystallized and polycrystalline silicon films was related to “volume random” and “surface columnar” crystallization phenomena, highlighting a linear relationship between the refractive index and the polysilicon volume fraction and, showing complex residual stress dependency with process conditions. Finally, by introducing the ratio V d/V c between the deposition and crystallization rates as a major parameter, different deposition behaviours and related semi-empirical relationships were defined in order to characterize fully the various properties of LPCVD silicon films (microstructure, polysilicon volume fraction, refractive index and residual stress) according to the chosen gaseous source, silane or disilane.

Properties of non‐stoichiometric nitrogen doped LPCVD silicon thin films

AbstractThe influence of nitrogen on the internal structure and so on the electrical properties of silicon thin films obtained by low‐pressure chemical vapor deposition (LPCVD) was studied using several investigation methods. We found by using Raman spectroscopy and SEM observations that a strong relationship exists between the structural order of the silicon matrix and the nitrogen ratio in film before and after thermal treatment. As a result of the high disorder caused by nitrogen on silicon network during the deposit phase of films, the crystallization phenomena in term of nucleation and crystalline growth were found to depend upon the nitrogen content. Resistivity measurements results show that electrical properties of NIDOS films depend significantly on structural properties. It was appeared that for high nitrogen content, the films tend to acquire an insulator behavior. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

High-Density Embedded Deep Trench Capacitors in Silicon With Enhanced Breakdown Voltage

This paper reports on the design, implementation, and characterization of high-density trench-refilled capacitors in complementary metal-oxide-semiconductor (CMOS) grade silicon (1-10 Omegacm). High aspect ratio trench-refilled capacitors offer a capacitance density improvement of three orders of magnitude compared to thin-film capacitors with the same die area and dielectric thickness. Also, dielectric materials such as low-pressure chemical vapor deposition (LPCVD) silicon oxide and silicon nitride are utilized to enhance the breakdown voltage of these devices. The high aspect ratio polysilicon and single crystal silicon process was utilized to implement these capacitors, giving a gap aspect ratio of . This ultrahigh vertical capacitance area achieves an ultralarge capacitance density without requiring thin-or high-k dielectric material. High-value capacitors of values ranging from 40 nF to 4 muF with capacitance density of 58 (nF/mm 2) were implemented in silicon as arrays of 170 mum-deep trenches. LPCVD silicon dioxide and silicon nitride were employed as dielectric materials to provide robust deposition inside the high aspect ratio trenches. Trench-refilled capacitors show quality factors (Q) of 230 and 8, respectively, at 45 nF and 4 muF capacitances. The breakdown voltage in trench-refilled capacitors with 35 nm-thick Si3N4 is recorded to be as high as 17-V, which is ~4x to 10x larger than that of BaTiO3 and PbZrxTi1 - xO3 (PZT) thin-film capacitors with the same dielectric thickness. Furthermore, the capacitances were measured over a temperature range of 25 to 155degC, showing less than 1.8% variation in 45 nF devices. This implies that trench-refilled capacitors are free from the very strong temperature sensitivity exhibited by most high-k materials.

다결정 실리콘 카바이드를 이용한 마이크로 유량센서

A thermal flow sensor has been fabricated and characterized, consisting of a center resistive heater surrounded by two upstream and one downstream temperature sensing resistors. The heater and temperature sensing resistors are fabricated from nitrogen-doped(n-type) polycrystalline silicon carbide(poly-SiC) deposited by LPCVD(low pressure chemical vapor deposition) on LPCVD silicon nitride films on a Si substrate. Cavities were etched into the Si substrate from the front side to create suspended silicon nitride membranes carrying the poly-SiC elements. One upstream sensor is located <TEX>$50{\mu}m$</TEX> from the heater and has a sensitivity of <TEX>$0.73{\Omega}$</TEX>/sccm with <TEX>${\sim}15\;ms$</TEX> rise time in a dynamic range of 1000 sccm. N-type poly-SiC has a linear negative temperature coefficient and a TCR(temperature coefficient of resistance) of <TEX>$-1.24{\times}10^{-3}/^{\circ}C$</TEX> from room temperature to <TEX>$100^{\circ}C$</TEX>.

On the impact of silicon nitride technology on charge trap NAND memories

The aim of this work is to study the impact of silicon nitride deposition/treatment technologies on charge trap (CT) nonvolatile memory performances. The authors have found that the technology modifies the charge trapping behavior with a one to one correlation between write/erase and charge retention characteristics. In particular, they used rapid thermal chemical vapor deposition techniques to obtain films with different compositions, but they were not able to improve CT performances with respect to standard low pressure chemical vapor deposition (LPCVD). Besides, an in situ steam generated treatment applied to standard LPCVD silicon nitride modifies the film properties inducing a lower programming efficiency, but improving charge retention characteristics.

Two microthermal shear stress sensors: surface micromachined and bulk-bonding micromachined

We describe two fabricated microthermal shear stress sensors by antiadhesion surface technology and anodic bulk-bonding technology. Two sensors are based on thermal transfer principles with adiabatic structures. The thermal sensor element is a titanium—platinum alloy resistor sputtered on the top of a low pressure chemical vapor deposited (LPCVD) silicon nitride diaphragm with an adiabatic vacuum cavity underneath. The surface micromachined thermal shear stress sensor uses microbumps on the silicon substrate in the sacrificial layer technology to prevent the silicon nitride diaphragm's stiction to the substrate. Microbumps formed by isotropic silicon etching in HNA (the system HF, HNO3, and HC2H3O2) are arrayed in several points on the silicon substrate with distances of 147 µm in the (200×250)-µm2×1.5-µm vacuum cavity. This cavity is formed by LPCVD silicon nitride film sealing with 30-Pa vacuum degree. The anodic bulk-bonding micromachined thermal shear stress sensor uses bulk silicon substrate etching and anodic bonding to form the (200×250)-µm2×400-µm high aspect ratio cavity with 5×10−2 Pa vacuum degree. The titanium platinum alloy resistor, (5×150)-µm2×0.2 µm, sputtered on the top of the 1.5-µm-thick LPCVD silicon nitride diaphragm with this bonding chamber, has a temperature coefficient of resistance (TCR) value of 0.33%/°C. According to the comparison of the adiabatic characteristics among three cases—a titanium platinum alloy resistor located over the high aspect ratio 5×10−2 Pa vacuum cavity, over the 30-Pa vacuum cavity, and directly on top of the substrate—the first case has the best adiabatic characteristic: the titanium platinum alloy resistor located over the 5×10−2-Pa vacuum cavity has the maximum thermal resistance of 5362 °C/W. Besides the sensor sensitivity performances, it has a comparatively short time constant with value of 0.1 ms under the constant current (CC) mode driving circuit.

Charging/discharging kinetics in LPCVD silicon nanocrystal MOS memory structures

The paper focuses on the peculiarities of charging/discharging kinetics and write/erase (W/E) window formation in nanocrystal metal-oxide semiconductor (MOS) non-volatile memory (NVM) structures prepared by low-pressure chemical vapor deposition (LPCVD) of amorphous silicon, followed by solid phase crystallization and thermal oxidation. It is generally known that the W/E window formation via pulse injection depends on the kinetics of carriers trapping (electrons and/or holes) in the nanocrystal NVM structure and consequently on the cumulative time of recharging bias application, i.e. pulse duration and number of applied pulses. In this work, we have shown that with the same cumulative time biasing but different charging pulse durations, the resulting W/E window width can be rather different, demonstrating a staircase window formation. This phenomenon is interpreted by a model of partial fast charge draining from the trapping sites in the vicinity of Si nanoclusters into the Si substrate. The detailed experimental investigation of charging/discharging kinetics of the considered structures in combination with computer simulations lead to the conclusion that there is a single process of negative charge trapping with a time constant of 235±35 ms and at least four processes of positive charge trapping with time constants distributed in the range from <10 ms to >10 s.

The Effect of LPCVD Silicon Nitride Deposition on the Si-SiO2 Interface of Oxidized Silicon Wafers

Low-pressure chemical vapor deposition (LPCVD) of silicon nitride on thermally oxidized silicon wafers changes the fundamental properties of the interface as a result of nitridation of the interface. This change results in an increase in the recombination rate of minority carriers at the silicon surface. The ammonia to dichlorosilane flow ratio during nitride deposition is a key parameter which affects the extent of this change. In addition, the recombination properties of the interface following nitride deposition are also influenced by charge in the nitride layer and by a change in the degree of hydrogen passivation of interface defects.

Hydrogen Reintroduction by Forming Gas Annealing to LPCVD Silicon Nitride Coated Structures

The effect of high-temperature anneals on low-pressure chemical-vapor deposited (LPCVD) /thermally grown stacks on silicon wafers has been studied. Annealing in a nitrogen atmosphere at 900 or for causes a substantial reduction in both and bond concentration in the nitride film and a significant degradation of surface passivation. Subsequent anneals in forming gas (95% Ar/5% ) at temperatures in the range lead to a gradual reformation of and bonds and an improvement in surface passivation. It is hypothesized that the chief mechanism responsible for the improvement in surface passivation is the passivation of defects at the interface with atomic hydrogen, supplied by the breaking of and bonds in the nitride film. Samples with stacks display excellent surface passivation following high-temperature forming gas anneals, indicating that such treatments can be used for photovoltaic applications, where surface passivation as well as good optical properties are important.

Characterization of SiC Passivation Using MOS Capacitor Ultraviolet-Induced Hysteresis

Different SiC thermal oxide passivation techniques were characterized using UV-induced hysteresis to estimate the fixed charge, Qf, and interface-trapped charge, Qit. Steam-grown oxides have a fixed charge density of Qf=-1x1012 cm-2, and a net interface-trapped charge density of Qit=4x1011cm-2. Addition of a thin low-pressure chemical-vapor deposited (LPCVD) silicon nitride layer decreased these parameters to Qf=-2x1011 cm-2 and Qit=4x1010 cm-2. Dry oxide shows a fixed charge density, Qf=-3x1012 cm-2 and interface-trapped charge density, Qit=4x1011 cm-2 which changes to Qf=+7x1010 cm-2 and Qit=1x1010 cm-2 with the addition of a LPCVD silicon nitride cap. Dry thermal oxide with a silicon nitride cap was used to passivate SiC MESFETs to achieve a power-added efficiency of 60% in pulsed operation at 3 GHz in Class AB bias conditions.

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.