Low-power Techniques Research Articles

Low-power WALTZ decoupling under magic-angle spinning NMR

Abstract. Heteronuclear low-power decoupling using the solution-state wideband alternating-phase low-power technique for zero-residual splitting (WALTZ) sequences has become quite popular in solid-state protein NMR and seems to work well. However, there are no systematic studies that characterize these sequences under magic-angle spinning (MAS) and give recommendations on which parameter should be used. We have studied in detail the use of WALTZ-16 and WALTZ-64 as low-power decoupling sequences under 100 kHz MAS by characterizing the resonance conditions analytically using numerical simulations and experiments on model substances. The recoupling heteronuclear resonance conditions between the modulation frequency of the sequences and the MAS frequency is the most important feature. Pulse lengths corresponding to areas with vanishing first-order heteronuclear recoupling are good candidates for efficient decoupling. We have characterized two such conditions which can be defined using the nutation frequency of the radio frequency (RF) field (ν1) and the spinning frequency (νr) by ν1=νr/10 and ν1=2νr/5, which both lead to narrow lines and are stable against RF-field variations and chemical-shift offsets. More such conditions might exist but were not investigated here.

Low power techniques for internet of things implementation: A review

The motive of designing a low-power system is to have a long battery life. One can carefully apply low-power design techniques to achieve low power consumption with proper system functioning to increase battery life. One such system where many devices are generally battery-operated and connected to the internet is the Internet of Things (IoT). IoT devices are used widely to gather data to propel actions and transmit the data for data analysis, connectivity, and automation. So much research is focused on IoT communication and computation in IoT devices, which increases power consumption. This survey explores low-power design strategies used at the architectural level. Additionally, it highlights the IoT features that give opportunities to apply low-power design methodologies to achieve less power consumption in IoT. Low-power design techniques are critical for the efficient functioning of Internet of Things (IoT) applications, where devices often operate in resource-constrained environments with limited power sources like batteries. Many applications of IoT are noticed including the domains such as industry, environment, and society, which are highly power-consuming because of the features such as computation, communication, security, and fault tolerance. Researchers have already reported the usefulness of many such techniques including architecture-level low-power design techniques. Still, it is observed that the work carried out is inadequate regarding power consumption, and communication bandwidth bottlenecks. In the present work, a rigorous literature survey is carried out based on low-power design techniques to support sustainable growth of IoT applications across various domains and power optimization.

A Taxonomy of Low-Power Techniques in Wearable Medical Devices for Healthcare Applications

Chronic diseases are the most prevalent and non-communicable health crisis globally. Most chronic disease patients require continuous physiological monitoring, using wearable technology for timely treatment, precise illness detection, and preventive healthcare. Nonetheless, efficient power management is required for such resource-constrained wearable devices. This work aims to analyze low-power techniques (LPTs) in wearable medical devices using a data-driven approach and identify novel approaches promising higher power savings. Through an intensive literature analysis, we identify the most relevant LPTs for minimizing power consumption in wearable devices for physiological monitoring while recognizing the barriers to adopting these techniques. As a result, a novel taxonomy based on the common characteristics of the LPTs is proposed, along with strategies for the combination of LPTs. Through our analysis, we propose possible enhancements in using LPTs and suggest mechanisms for the medical device industry to facilitate their adoption. Overall, our proposed strategies guide the use of LPTs on wearable medical devices toward continuous physiological monitoring.

ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

Low power techniques are becoming more important as portable digital applications expand quickly and demand high speed and low power consumption. The ALU is the most crucial and essential component of a central processing unit, as well as numerous embedded systems and microprocessors. Designing a 32-bit ALU that combines an arithmetic unit and a logical unit is the task at hand. The logic unit will do logic operations AND, OR, XOR, and XNOR with the aid of the recommended CMOS technology, while the arithmetic unit will do the arithmetic operations addition, subtraction, increment, and buffering operation. The arithmetic unit is constructed using the 4x1 MUX, 2x1 MUX, and full adder, and the 4x1 MUX, required logic gates, and 4x1 MUX are employed to create the logical unit. Using Cadence Virtuoso Gpdk 180nm Technology, the results of the simulation of the 32-bit ALU, the ideal delay, and the Power were calculated.

Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

A High-Performance and Ultra-Low-Power Accelerator Design for Advanced Deep Learning Algorithms on an FPGA

This article addresses the growing need in resource-constrained edge computing scenarios for energy-efficient convolutional neural network (CNN) accelerators on mobile Field-Programmable Gate Array (FPGA) systems. In particular, we concentrate on register transfer level (RTL) design flow optimization to improve programming speed and power efficiency. We present a re-configurable accelerator design optimized for CNN-based object-detection applications, especially suitable for mobile FPGA platforms like the Xilinx PYNQ-Z2. By not only optimizing the MAC module using Enhanced clock gating (ECG), the accelerator can also use low-power techniques such as Local explicit clock gating (LECG) and Local explicit clock enable (LECE) in memory modules to efficiently minimize data access and memory utilization. The evaluation using ResNet-20 trained on the CIFAR-10 dataset demonstrated significant improvements in power efficiency consumption (up to 22%) and performance. The findings highlight the importance of using different optimization techniques across multiple hardware modules to achieve better results in real-world applications.

Network on Chip and Its Low Power Techniques

The advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques. Key Words: Network-On-Chip, System-On-Chip, latency and scalability

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

The study proposes a hybrid data driven clock gating and data gating technique which is applied to ALU in RISC-V. By doing so, the proposed low power technique can improve the power saving efficiency. The proposed low power technique is compared with various low power techniques such as latch-free based clock gating, latch-based clock gating, single data driven clock gating, and single data gating. The results show that the proposed low power ALU saves 46.67% power consumption compared to original ALU. The proposed ALU also shows better saving power than the latch-free based clock gating, latch-based clock gating, sdata driven clock gating, and data gating from 10.84% to 22.23%. The comparison is also implemented on CPU which consists of memory, ALU and control unit. The proposed low power CPU saves 12.11% at least compared to the original CPU. However, the proposed low power CPU is reduced to 15.1% maximum frequency operation compared to the original CPU. The area overhead of the proposed ALU also increased to 33 LUTS (8.2%) and 2 registers (1.6%) compared to the original ALU.

A Study of Advancing Ultralow-Power 3D Integrated Circuits with TEI-LP Technology and AI-Enhanced PID Autotuning

The 3D integrated circuit (3D-IC) is garnering significant attention from academia and industry as a key technology leading the post-Moore era, offering new levels of efficiency, power, performance, and form-factor advantages to the semiconductor industry. However, thermal management in 3D-ICs presents a critical challenge that must be overcome to ensure prosperity for this technology. Unlike traditional thermal management solutions that perceive heat generation in 3D-ICs negatively and aim to eliminate it, this paper proposes, for the first time, a thermal management method that positively utilizes heat to achieve low-power operation in 3D-ICs. This approach is based on a novel discovery that circuits can reduce power consumption at higher temperatures by leveraging the temperature effect inversion (TEI) phenomenon in ultralow-voltage (ULV) operating circuits, a characteristic of low-power techniques (TEI-LP techniques). Along with a detailed explanation of this discovery, this paper introduces new thermal management technologies for practical application in 3D-ICs. Furthermore, to achieve optimal energy efficiency with the proposed technology, we develop a temperature controller essential for this purpose. The developed controller is a deep learning-based PID autotuner. This paper proves the theoretical validity of the AI control algorithm designed for this purpose and demonstrates the functional correctness and power-saving effectiveness of the developed controller through intensively conducted simulations.

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

Recent Advances in Acoustofluidics for Point-of-Care Testing.

Point-of-care testing (POCT) has played important role in clinical diagnostics, environmental assessment, chemical and biological analyses, and food and chemical processing due to its faster turnaround compared to laboratory testing. Dedicated manipulations of solutions or particles are generally required to develop POCT technologies that achieve a "sample-in-answer-out" operation. With the development of micro- and nanotechnology, many tools have been developed for sample preparation, on-site analysis and solution manipulations (mixing, pumping, valving, etc.). Among these approaches, the use of acoustic waves to manipulate fluids and particles (named acoustofluidics) has been applied in many researches. This review focuses on the recent developments in acoustofluidics for POCT. It starts with the fundamentals of different acoustic manipulation techniques and then lists some of representative examples to highlight each method in practical POC applications. Looking toward the future, a compact, portable, highly integrated, low power, and biocompatible technique is anticipated to simultaneously achieve precise manipulation of small targets and multimodal manipulation in POC applications.

Aerosol absorption measurement by a Shack-Hartmann wavefront sensor.

Researchers at the U.S. Army Space and Missile Defense Command have developed a method for quantifying high energy near-infrared (NIR) laser heating of air resulting from laser absorption of suspended dry aerosols in a controlled environmental chamber. The measurements were accomplished using an ISO standard test dust and NIR high energy laser using a Shack-Hartmann wavefront sensor. This paper presents the methodology of the measurement as well as the quantitative reconstruction of the air temperature profile, absorption efficiency, and imaginary refractive index of the aerosol. The resulting measurement of the aerosol imaginary index of refraction was significantly lower than values typically found in the literature from measurements using low power techniques. These findings are in general agreement with other recently published works that have found that previously published values of mineral dust aerosols could be significantly overestimated.

An Implantable Bio-Signal Sensor SoC with Low-Standby-Power 8K-Bit SRAM for Continuous Long-Term Monitoring

Individualized treatment of chronic diseases opens up great opportunities for implantable biosensor systems capable of tracking vital signals over long periods of time. To this end, low-power techniques in standby mode and the efficient utilization of storage space will be important issues for the implementation of such rechargeable implants with a built-in memory. This paper presents key circuit techniques, including a leakage-current-based clock generator that eliminates the need for an internal reference clock source, a low-standby-power 8Kbit SRAM with negative wordline and dynamic supply voltage scaling, and an adaptive sensing scheme to improve storage space utilization. When implemented with commercial 180 nm CMOS technology for the circuit simulation, approximately 70% (100 nW) of power dissipation was reduced from internal clock source, about 70% of power consumed by 8Kbit SRAM was saved, and the storage space utilization was improved by about 42.8%. In the end, the proposed implantable biosensor SoC consumes about 82.5 nW of standby power, saving about 42% from the previous approach and can last for 2.5 days using a 5 uAh thin-film battery (CYMBET® 1.7 × 2.2 mm2).

A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS

Abstract: Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

Low Power Embedded SoC Design

Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.

A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias

This work presents a 16kB ultra-low power (ULP) SRAM macro in 28nm FD-SOI with high energy efficiency in active mode and ultra-low leakage (ULL) in sleep mode, embedded in the SleepRider micro-controller unit (MCU) intended for IoT edge applications. The proposed SRAM integrates custom 7T ULL bitcells based on negative differential resistance (NDR) structures and a pMOS-only write port, achieving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> lower area than previous NDR-based bitcells. A dual-supply strategy combined with negative-wordline write-assist concurrently provides worst-case data retention and correct write operations, up to the 64-MHz MCU target frequency. The SRAM macro periphery combines several low-power techniques to extract the full potential of the novel 7T bitcells, reaching an unprecedented speed-energy-leakage optimum with only 2.5% area overhead. Adaptive forward body biasing (FBB) further improves active mode performance while ensuring robustness against PVT variations. Measurement results showcase a minimum energy point of 0.78pJ per 32b access (assuming 50% read/write) at 0.5V and 64MHz. Moreover, leakage power drops from 296nW/kB at 0.5V in idle conditions to 0.23nW/kB in sleep at the 0.46V data retention voltage (DRV), yielding more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000\times $ </tex-math></inline-formula> leakage reduction. As such, the proposed SRAM achieves an excellent trade-off between area, leakage and energy in the 10-to-100MHz frequency range.

The design of a low-power 4-bit barrel shifter for a current steering DAC using optimized multiplexers in 65 nm technology

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

A Reconfigurable CNN-Based Accelerator Design for Fast and Energy-Efficient Object Detection System on Mobile FPGA

In limited-resource edge computing circumstances such as on mobile devices, IoT devices, and electric vehicles, the energy-efficient optimized convolutional neural network (CNN) accelerator implemented on mobile Field Programmable Gate Array (FPGA) is becoming more attractive due to its high accuracy and scalability. In recent days, mobile FPGAs such as the Xilinx PYNQ-Z1/Z2 and Ultra96, definitely have the advantage of scalability and flexibility for the implementation of deep learning algorithm-based object detection applications. It is also suitable for battery-powered systems, especially for drones and electric vehicles, to achieve energy efficiency in terms of power consumption and size aspect. However, it has the low and limited performance to achieve real-time processing. In this article, optimizing the accelerator design flow in the register-transfer level (RTL) will be introduced to achieve fast programming speed by applying low-power techniques on FPGA accelerator implementation. In general, most accelerator optimization techniques are conducted on the system level on the FPGA. In this article, we propose the reconfigurable accelerator design for a CNN-based object detection system on the register-transfer level on mobile FPGA. Furthermore, we present RTL optimization design techniques that will be applied such as various types of clock gating techniques to eliminate residual signals and to deactivate the unnecessarily active block. Based on the analysis of the CNN-based object detection architecture, we analyze and classify the common computing operation components from the Convolutional Neuron Network, such as multipliers and adders. We implement a multiplier/adder unit to a universal computing unit and modularize it to be suitable for a hierarchical structure of RTL code. The proposed system design was tested with Resnet-20 which has 23 layers and it was trained with the dataset, CIFAR-10 which provides a test set of 10,000 images in several formats, and the weight data we used for this experiment was provided from Tensil. Experimental results show that the proposed design process improves the power efficient consumption, hardware utilization, and throughput by 16%, up to 58%, and 15%, respectively.

Sorter Design with Structured Low Power Techniques

Sorter Design with Structured Low Power Techniques

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.