High-speed Low-power Applications Research Articles

Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications

Synergistic m_GDI-Based ALU Design Using CMOS and VTEAM Memristor Model for Low-Power High-Speed Applications

Design and Analysis of CMOS Dynamic Comparator for High-Speed Low-Power Applications Using Charge Sharing Technique

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V.

Heterojunction tunnel field-effect transistor suitable for high-speed low-power applications

Heterojunction tunnel field-effect transistor suitable for high-speed low-power applications

Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC & Analog Performance Projections

This work exclusively illustrates dual-metal double gate Ge pocket tunnel field effect transistor (DMG-DG-Ge pocket TFET) with hetero gate dielectric. This structure includes dual-metal gate and hetero-dielectric as well. Extensive TCAD simulation analysis is carried out to illustrate how the device transfer characteristics changes in different regions with respect to various parameters such as, the work-function of tunneling gate and auxiliary gate variations, lengths ratio of tunneling gate and auxiliary gate, and the dielectric constants of homo/hetero dielectrics involved. Here, optimization of dual metal gate work-function is done along with dual gate metal length ratio. To optimize the device behavior hetero gate dielectric HfO2 and SiO2 are considered over the source-channel interface and channel-drain interface, respectively. The enhanced device transfer characteristics obtained are explained and verified with the energy band diagram and tunneling length. The reported device structure achieves ION/IOFF = 5.05 × 1011 and sub-threshold slope (SS) as 15.9425 mV/decade along with the reduced ambipolar current. An increase in ION/IOFF ratio by the order of four as compared to Ge-pocket TFET, is reported with reasonably high ON current for sub 0.5 V supply. This enables the device for low power applications. In addition to this, for the complete analog and RF characterization of the proposed device structure, transconductance, parasitic capacitance, cut-off frequency, intrinsic delay, energy-delay product, transconductance generation factor etc. are also illustrated in detail here. Further, the energy efficiency of the device is also analyzed and justifies for its low power high-speed applications.

A new boosted charge-steering latch for high-speed low-power applications

This paper presents a new high-speed low-power charge-steering latch, using a boosting technique for the tail capacitor, which is charged reversely in the reset phase. This technique decreases the source node voltage of the differential pair, which improves the output voltage swing. Analysis and post-layout simulation results of the proposed boosted charge-steering latch (BCS), in 65 nm CMOS technology, illustrate that for the same output swing and with about 28% tail capacitor of the conventional charge-steering latch, the maximum operating frequency is increased by about 12%. In the case of the same tail capacitor, the BCS latch gives the output swing of about 30% higher than that of conventional one for the low to moderate input swing, while its maximum operating frequency is about 20% higher.

Design of PMOS and NMOS Input Folded Cascode Amplifier using 180nm SCL Technology Node for Low Power Application

This paper presents the details design and simulation of the Folded Cascode amplifier using Source-Coupled-Logic (SCL) technology node for both the P-Type Metal Oxide Semiconductor (PMOS) and N-Type Metal Oxide Semiconductor (NMOS) input. The different way to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like open loop gain, Unity Gain Bandwidth (UGB) and Phase Margin (PM) are compared for both the NMOS and PMOS input fully differential folded cascode op-amp circuit are discussed and finally we have got after performance analysis that NMOS input fully differential folded cascode op-amp is the best choice for low power high speed application like in pipeline Analog to Digital (ADC). The circuit has been simulated using cadence virtuoso tool in 0.18μm SCL technology node.

A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

A Novel high-speed low power 9T full adder

In modern era, low power high speed applications become one of the prime areas of focus for digital VLSI applications. Addition is a vital arithmetic operation and it acts as the main building block for synthesizing all other operations. A low power high speed full adder is introduced using 9 transistors. It consists of 3 modules, XOR module, sum module and carry module. While comparing with other designs it has a significant reduction in delay, power and hence the power delay product. The circuit is implemented and simulated using Cadence Virtuoso tool. Entire design is divided into three modules. Module 1 consists of modified XOR circuit which has only four transistors. Module 2 and Module 3 are SUM and CARRY design respectively. CARRY OUT of full adder circuit is made up by using Gate Diffusion Input (GDI)logic whereas the SUM is made using another XOR design. The design was implemented using cadence tool and power, delay and PDP are found to be very small as compared with otherdesigns.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Performance Comparison Between PCB-Stator and Laminated-Core-Stator-Based Designs of Axial Flux Permanent Magnet Motors for High-Speed Low-Power Applications

Gearless and small motors operating at speeds above 10 000 rpm are finding many applications nowadays. Axial flux permanent magnet (AFPM) motors are compact and lightweight compared to radial flux motors and hence, are considered for various high-speed applications. Eliminating the stator core minimizes the associated high-frequency losses, and hence, coreless AFPM motor can be an option for high-speed applications. Furthermore, the coreless AFPM motor design minimizes the cogging torque and the axial attraction force between the stator core and the rotor magnets. However, the reduction of flux linkage in the stator windings is a challenge in coreless AFPM motor. In this article, the advantages and disadvantages of the printed circuit board (PCB)-based AFPM motor for high-speed, low-power applications are investigated. A detailed performance comparison of the PCB-based coreless AFPM motor and the AFPM motor with the laminated stator core is made. Finite-element analysis is carried out for the electromagnetic, mechanical, and thermal comparison of the two motors and the simulation results are presented. Finally, motor prototypes are fabricated and are tested to ascertain the simulation results.

LG = 20 nm High Performance GaAs Substrate Based Metamorphic Metal Oxide Semiconductor High Electron Mobility Transistor for Next Generation High Speed Low Power Applications

<i>L</i>_G = 20 nm High Performance GaAs Substrate Based Metamorphic Metal Oxide Semiconductor High Electron Mobility Transistor for Next Generation High Speed Low Power Applications

A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation

An 8-bit 1-GS/s hybrid analog-to-digital converter (ADC) for high-speed low-power applications is introduced. It has a subranging architecture with a 3-bit flash ADC as a first stage and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. In each channel, a merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) performs the sampling and residue generation for the subranging operation. The effects of the parasitic capacitances on the SHDAC linearity are analyzed, and a linearity correction method is introduced to enable power-efficient high-speed operation in the presence of parasitics because the design approach allows reducing the sampling capacitance in the SHDAC. Furthermore, the sampling network configuration incorporates an error reduction technique to alleviate the clock feedthrough of bootstrap switches. The offsets of the comparators in the flash ADC are calibrated using a built-in reference signal via an extra sampling channel. According to postlayout simulations at 1 GS/s in 130-nm CMOS, the ADC has an effective number of bits higher than 7.37 bits up to the Nyquist frequency while consuming 13.3 mW from a 1.2-V supply.

20 nm high performance novel MOSHEMT on InP substrate for future high speed low power applications

In this work, the DC and RF performance of a 20 nm gate length novel metal oxide semiconductor high electron mobility transistor (MOSHEMT) on InP substrate is studied using Sentaurus TCAD tool. The proposed MOSHEMT device features heavily doped In0.52Ga0.48As source/drain regions, delta doped planes on both sides of the In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel, a multi layer cap and a very thin layer of HfO2 as gate dielectric. The TCAD simulation results obtained at room temperature using physics based carrier transport model indicates that the 20 nm gate length proposed MOSHEMT device is capable of providing a peak drain current of 2860 mA/mm at VDS = 0.6 V and the peak transconductance obtained for the proposed device is 2890 mS/mm. The fT and fmax obtained for the Lg = 20 nm proposed MOSHEMT on InP substrate are 537 GHz and 631 GHz respectively. At 300 K, the measured Hall mobility of the electrons in the quantum well channel is 11620 cm2/V. The on state resistance (RON), subthreshold swing (SS) and drain induced barrier lowering (DIBL) obtained for the Lg = 20 nm proposed InP-MOSHEMT are 105 Ω μm, 160 mV/dec and 178 mV/V respectively. These devices are undoubtedly, the most suitable candidates for future high speed, low power post silicon logic applications.

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications

Design and Analysis of an 8T Read Decoupled Dual Port SRAM Cell for Low Power High Speed Applications

A new efficient SC integrator scheme for high-speed low-power applications

A new solution to implement efficient switched-capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35−µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.

A differential binary message-passing LDPC decoder

In this paper, we propose a binary message-passing algorithm for decoding low-density parity-check (LDPC) codes. The algorithm substantially improves the performance of purely hard-decision iterative algorithms with a small increase in the memory requirements and the computational complexity. We associate a reliability value to each nonzero element of the code's parity-check matrix, and differentially modify this value in each iteration based on the sum of the extrinsic binary messages from the check nodes. For the tested random and finitegeometry LDPC codes, the proposed algorithm can perform as close as about 1 dB and 0.5 dB to belief propagation (BP) at the error rates of interest, respectively. This is while, unlike BP, the algorithm does not require the estimation of channel signal to noise ratio. Low memory and computational requirements and binary message-passing make the proposed algorithm attractive for high-speed low-power applications.

Improved 32-bit conditional sum adder for low-power high-speed applications

This paper presents an improved 32-bit conditional sum adder. Due to architectural modification, the improved adder only selects and transmits carry signals; it therefore is named conditional carry adder (CCA). This 32-bit adder focuses on reducing the numbers of internal nodes and logical gates, while maintaining high speed. The 32-bit conditional sum adder uses 186 multiplexers, and the proposed 32-bit CCA only uses 129 multiplexers. Consequently, the proposed adder is attractive for use in low-power arithmetic systems. Conventional single-end static CMOS and differential-end CPL circuits were used to implement and compare the proposed 32-bit CCA. Experimental and control chips were designed and fabricated using 0.5μm CMOS technology. Simulations and measurements under various supply voltages showed that the 32-bit CCA achieved high performance in low-voltage high-speed applications.

Low-power pipeline ADC for wireless LANs

In this paper, a 10-bit 40-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 12 mW was achieved by using a time-interleaved and pipelined architecture with shared operational amplifiers. This circuit was fabricated in a 2.5-V 0.25-/spl mu/m technology with metal-oxide-metal capacitors. Experimental results are within design ranges and are in good agreement with simulation data. It turns out that the proposed Nyquist-rate ADC provides a potential solution for low-power high-speed applications, e.g., wireless LANs.

Low-power high-speed operation of submicron InP-InGaAs SHBTs at 1 mA

Scaling of submicron InP-InGaAs HBTs is investigated for low-power high-speed applications in mixed signal circuits. Device performance for transistors fabricated with a 0.5-μm emitter width and varying emitter lengths are studied. The 0.5 μm×2 μm devices yielded excellent low-current RF performance, with an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =173 GHz and an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =187 GHz at 1 mA, the highest values reported for InP-based devices to date.