Low-power Hardware Implementation Research Articles

Practical hardware demonstration of a multi-sensor goal-oriented semantic signal processing and communications network

Recent advancements in machine learning, particularly real-time extraction of rich semantic information, reshape signal processing techniques and related hardware architectures. To address the highly challenging requirements of next-generation signal processing applications in networked platforms, we investigate low-power hardware implementation alternatives for a multi-sensor, goal-oriented semantic communications network. Specifically, we focus on cost-effective Raspberry Pis in a multi-sensor semantic video communication application, showcasing adaptability from traditional CPU/GPU configurations. Additionally, we provide a preliminary investigation on implementing semantic extraction tasks through in-memory computation using memristor arrays to further emphasize the potential future of low-power low-cost semantic signal processing. Hardware demonstrations using Raspberry Pi 4Bs and simulations with in-memory computation architectures offer promising hardware architectures with cost-effective and low-power sensor alternatives to the next-generation semantic signal processing applications and semantic communication systems.

Support vector machines implementation over integers modulo-M and Residue Number System

In low-power hardware implementations for classification algorithms, it is often essential to use physical resources efficiently. In this sense, the use of modulo-M integer operations instead of floating-point arithmetic, can lead to better performance, especially when M represents the dynamic range of an arithmetic block of the Residue Number System (RNS) [1,2]. Following this premise, this work is aiming to provide a methodology for implementing a classifier, specifically a Support Vector Machine (SVM) [3], using modulo-M integers and proposing a method for the use of Residue Number System.

Event-Based Optical Flow Estimation with Spatio-Temporal Backpropagation Trained Spiking Neural Network.

The advantages of an event camera, such as low power consumption, large dynamic range, and low data redundancy, enable it to shine in extreme environments where traditional image sensors are not competent, especially in high-speed moving target capture and extreme lighting conditions. Optical flow reflects the target's movement information, and the target's detailed movement can be obtained using the event camera's optical flow information. However, the existing neural network methods for optical flow prediction of event cameras has the problems of extensive computation and high energy consumption in hardware implementation. The spike neural network has spatiotemporal coding characteristics, so it can be compatible with the spatiotemporal data of an event camera. Moreover, the sparse coding characteristic of the spike neural network makes it run with ultra-low power consumption on neuromorphic hardware. However, because of the algorithmic and training complexity, the spike neural network has not been applied in the prediction of the optical flow for the event camera. For this case, this paper proposes an end-to-end spike neural network to predict the optical flow of the discrete spatiotemporal data stream for the event camera. The network is trained with the spatio-temporal backpropagation method in a self-supervised way, which fully combines the spatiotemporal characteristics of the event camera while improving the network performance. Compared with the existing methods on the public dataset, the experimental results show that the method proposed in this paper is equivalent to the best existing methods in terms of optical flow prediction accuracy, and it can save 99% more power consumption than the existing algorithm, which is greatly beneficial to the hardware implementation of the event camera optical flow prediction., laying the groundwork for future low-power hardware implementation of optical flow prediction for event cameras.

An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation

A spatiotemporal contextual learning and memory network (STCLMN) model was proposed based on the hippocampal CA1 network using the difference equations suitable for digital computer simulations. However, the inherent capability of handling and processing of continuous-time asynchronous signals (spikes) cannot be fully employed in the STCLMN model. Furthermore, digital circuit implementation of the STCLMN is not suitable for real-time edge applications, wherein small size, low power consumption, and real-time learning capability are necessary. Therefore, this study extends the original STCLMN model using a set of differential equations to overcome the above problems encountered by STCLMN for asynchronous circuit implementation. The minimum accuracy required for a compact and low-power hardware implementation of the proposed model is then investigated. The validity and feasibility of the proposed model are confirmed through numerical simulations and experiments with a small mixed analog/digital circuit based on the investigated accuracy. In this study, LIF neurons are used because of their ease of circuit implementation. The proposed eSTCLMN model would enable an efficient circuit implementation of an asynchronous spiking neural network with spatiotemporal contextual one-shot learning and memory.

“Ghost” and Attention in Binary Neural Network

As the memory footprint requirement and computational scale concerned, the light-weighted Binary Neural Networks (BNNs) have great advantages in limited-resources platforms, such as AIoT (Artificial Intelligence in Internet of Things) edge terminals, wearable and portable devices, etc. However, the binarization process naturally brings considerable information losses and further deteriorates the accuracy. In this article, three aspects are introduced to better the binarized ReActNet accuracy performance with a more low-complex computation. Firstly, an improved Binarized Ghost Module (BGM) for the ReActNet is proposed to increase the feature maps information. At the same time, the computational scale of this structure is still kept at a very low level. Secondly, we propose a new Label-aware Loss Function (LLF) in the penultimate layer as a supervisor which takes the label information into consideration. This auxiliary loss function makes each category’s feature vectors more separate, and improve the final fully-connected layer’s classification accuracy accordingly. Thirdly, the Normalization-based Attention Module (NAM) method is adopted to regulate the activation flow. The module helps to avoid the gradient saturation problem. With these three approaches, our improved binarized network outperforms the other state-of-the-art methods. It can achieve 71.4% Top-1 accuracy on the ImageNet and 86.45% accuracy on the CIFAR-10 respectively. Meanwhile, its computational scale OPs is the least 0.86×10⁸ compared with the other mainstream BNN models. The experimental results prove the effectiveness of our proposals, and the study is very helpful and promising for the future low-power hardware implementations.

Highly-accurate binary tiny neural network for low-power human activity recognition

An ultra low power hardware implementation of Human Activity Recognition systems imposes very tight constraints. Therefore it requires a very thoughtful balancing between highly accurate results and the reduction of the allocated physical resources. Deep Learning models provide the highest accuracies, however their typical computational complexity and memory requirements are not easily deployable in handheld or wearable devices which embody very constrained memory and computation capabilities. In this work, we introduce a new HAR system built with a new Hybrid Binarized Neural Network suitable for a very compact and ultra low-power hardware implementation. The system receives data from MEMS based inertial sensors and makes the acquisitions independent from the sensor spatial orientation and the gravity acceleration signal. The system has been trained and validated on the PAMAP2 and SHL dataset. In both cases, it achieves accuracies higher than 99% in the best case, with different input sensor configurations. A custom circuit has been implemented, which extensively shares circuitry between the different functional sub-modules of the system to minimize the amount of mapped physical resources. The FPGA implementation on a Xilinx Artix 7 achieves a total power dissipation of 72 mW and occupies 6788 LUTs.

Low-Power Approximate Logarithmic Squaring Circuit Design for DSP Applications

The squaring function is widely used in Digital Signal Processing (DSP). There are many DSP applications with noisy inputs for which simplifying approximations of the squaring function implementation have a minor impact on the output quality, while permitting significant reductions in the hardware cost. This article proposes a Low-Error Squaring Function (LESF) and its low-power hardware implementation. Unlike the existing logarithmic squaring functions, LESF benefits from a double-sided error distribution and, consequently, error cancellation in larger calculations. LESF approximates a base-2 logarithmic function with a linear polynomial, i.e., <inline-formula><tex-math notation="LaTeX">$\mathrm{log_2}\;f(x) \approx ax+b$</tex-math></inline-formula> . Since input <inline-formula><tex-math notation="LaTeX">$b$</tex-math></inline-formula> in this sum is a constant, LESF replaces the conventional full-adder with a compact specialized adder for hardware efficiency. Our simulation results show that the 16-bit LESF is 23.23 percent more accurate (in the mean relative error distance) than the baseline Mitchell approximate logarithmic squaring function while being 1.8× faster and 39 percent more energy-efficient. LESF and other logarithmic squaring functions are evaluated for the square-law detector application. LESF is shown to be more than 3× more accurate in this application (with respect to the Euclidean distance) than the next most accurate design in the literature, which uses an iterative error compensation technique.

Low-Power Hardware Implementation of a Support Vector Machine Training and Classification for Neural Seizure Detection.

In this paper, a low power support vector machine (SVM) training, feature extraction, and classification algorithm are hardware implemented in a neural seizure detection application. The training algorithm used is the sequential minimal optimization (SMO) algorithm. The system is implemented on different platforms: such as field programmable gate array (FPGA), Xilinx Virtex-7 and application specific integrated circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. The implemented training hardware is introduced as an accelerator intellectual property (IP), especially in the case of large number of training sets, such as neural seizure detection. Feature extraction and classification blocks are implemented to achieve the best trade-off between sensitivity and power consumption. The proposed seizure detection system achieves a sensitivity around 96.77% when tested with the implemented linear kernel classifier. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is improved by a factor of 2X when compared with the FPGA counterpart.

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS

Machine learning has become ubiquitous in applications including object detection, image/video classification, and natural language processing. While machine learning algorithms have been successfully used in many practical applications, accurate, fast, and low-power hardware implementations of such algorithms is still a challenging task, especially for mobile systems such as Internet of Things (IoT), autonomous vehicles, and smart drones. This paper presents an energy-efficient programmable ASIC accelerator for object detection. Our ASIC accelerator supports multi-class (e.g., face, traffic sign, car license plate, and pedestrian) that are programmable, many-object (up to 50) in one image with different sizes (17-scale support with 6 down-/11 up-scaling), and high accuracy (AP of 0.87/0.81/0.72/0.76 for FDDB/AFW/BTSD/Caltech datasets). We designed an integral channel detector with 2,000 classifiers for rigid boosted templates, where the number of stages used for classification can be adaptively controlled depending on the content of the search window. This can be implemented with a more modular hardware, compared to support vector machine (SVM) and deformable parts model (DPM) designs. By jointly optimizing the algorithm and the efficient hardware architecture, the prototype chip implemented in 65nm CMOS demonstrates real-time object detection of 20–50 frames/s with low power consumption of 22.5–181.7 mW (0.54–1.75 nJ/pixel) at 0.58–1.1 V supply.

(Invited) Electrochemically-Tunable and Low-Power 2D Synapses for Neuromorphic Computing

Inspired by the human brain, which is better at complex tasks such as pattern recognition than even supercomputers with much better efficiency, neuromorphic computing has recently attracted much research attention. Biological neural networks employ analog changes in neural connections strength (i.e. synaptic weight) during the decision-making and learning processes, in contrast to modern computers that use digital ‘0’ and ‘1’ for computation. However, majority of the current research efforts towards developing artificial synapses are based on digital technology with the binary SRAM, which consists 8 transistors, making it impractical to scale up the system to the level of complexity we need due to constraints in power and area. Recently, emerging nanoelectronics such as phase-change memory (PCM), oxide-based resistive random access memory (RRAM), metal-ion based electrochemical metallization memory (ECM), spin torque transfer (STT) RAM, ferroelectric FeRAM, and nano-devices have been studied for neuromorphic computing. While some of these approaches especially PCM and RRAM have demonstrated promising results to lower the power consumption and speed up the learning, they still suffer from critical issues such as insufficient precision, non-linear behaviors, and large device variations. In this work, we present a novel approach to build electrochemically-tunable, two-dimensional (2D) synapses with excellent controllability (~0.25% ΔR per switching), good energy efficiency (~500 fJ per switching), symmetric resistance response, and a rare combination of low-power programming and good retention. In our 2D synapses, the channel conductance, representing the synaptic weight in a biological synapse, can be modulated by controlling the concentration of ions between layers of graphene through a process called electrochemical intercalation. The major advantage in our approach is that we can achieve reversible and precise programming of the 2D device’s conductance to mimic synaptic plasticity with low power consumption. Unlike typical memory devices, the programming and storage mechanisms in our electrochemical synapses are decoupled, allowing us to achieve both low-power switching and good retention properties. While electrochemical intercalation has been widely used in rechargeable Li ion batteries (LIBs), this is the first demonstration of a 2D electrochemical analog memory for synaptic devices. We choose graphene in this work because graphite is a common anode material for Li ion batteries (LIBs), with good compatibility and well-characterized behaviors for Li intercalation, as illustrated in our galvanostatic discharge and in-situ Raman measurements. Through tuning the electrochemical potential of graphene, we can modulate the Li concentration and thus the electrical conductance of graphene in a continuous fashion. We perform pulse measurements (50-pA, 10-ms) to emulate the excitatory and inhibitory behavior of synapse, where we achieve ~0.25% change of channel resistance ΔR per pulse. This decrease (increase) in resistance, mimicking an increase (decrease) in synaptic weight of an excitatory (inhibitory) synapse, is the result of an increase (decrease) of Li concentration in graphene. We also achieve long-term potentiation and depression (increase and decrease in synaptic weight) through applying a series of intercalating and de-intercalating pulses. We reliably and reversibly program the graphene synapse into over 400 discrete states over our operating range. The resistance response is highly symmetric and linear. Lastly, we demonstrate spike-timing-dependent plasticity (STDP) in our synapse, where the change in resistance depends on the timing difference Δt between the pulses – similar to the biological phenomenon that the effectiveness of repeated learning depends on the duration of the gap between each stimulation. In summary, we develop an electrochemical, 2D synaptic device with low energy efficiency (500 fJ/synaptic event), precise control over synaptic conductance (0.25% ΔR per step), and good cycling performance. We demonstrate basic neuromorphic functionalities such as short-term and long-term plasticity, as well as spike-timing-dependent plasticity. This work can lead to the low-power hardware implementation of neural networks for neuromorphic computing as well as tunable 2D electronics where the material properties can be precisely engineered.

Embedded Mission Decision-Making based on Dynamic Decision Networks in SoPC Platform

This paper tackles a Bayesian Decision Making approach for unmanned aerial vehicle (UAV) mission that allows UAV to quickly react to unexpected events under dynamic environments. From online observations and the mission state-ment, the proposed approach is designed by means of Dynamic Bayesian Networks (DBN) arising from the safety or performance failures analysis. After proposing a DBN model, a probabilistic approach based on Multiple-Criteria Decision-Making (MCDM) is then applied to find the best configuration reaching a balance between performance and energy consumption, thus decide which tasks will be implemented as SW and which as HW execution units, regarding the mission requirement. The proposal UAV mission decision-making is three-pronged, providing: (1) real time image pre-processing of sensor observations; (2) temporal and probabilistic approach based on Bayesian Networks to continuously update the mission plan during the flight; and (3) low-power hardware and software implementations for online and real time embedded Decision Making using Xilinx System on Programmable Chip (SoPC) platform. The proposed approach is then validated with a practical case UAV mission planning using the proposed dynamic decision-maker implemented on embedded system based on a hybrid device.

A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers

Current deep learning approaches have been very successful using convolutional neural networks trained on large graphical-processing-unit-based computers. Three limitations of this approach are that (1) they are based on a simple layered network topology, i.e., highly connected layers, without intra-layer connections; (2) the networks are manually configured to achieve optimal results, and (3) the implementation of the network model is expensive in both cost and power. In this article, we evaluate deep learning models using three different computing architectures to address these problems: quantum computing to train complex topologies, high performance computing to automatically determine network topology, and neuromorphic computing for a low-power hardware implementation. We use the MNIST dataset for our experiment, due to input size limitations of current quantum computers. Our results show the feasibility of using the three architectures in tandem to address the above deep learning limitations. We show that a quantum computer can find high quality values of intra-layer connection weights in a tractable time as the complexity of the network increases, a high performance computer can find optimal layer-based topologies, and a neuromorphic computer can represent the complex topology and weights derived from the other architectures in low power memristive hardware.

Low power hardware implementations for network packet processing elements

The real world network packet processing demands high performance hardware to achieve the required speed. This paper proposes the various hardware optimizations on payload matching, packet classification, and backplane switch interconnects by allowing architectural changes in the existing designs. Here, asynchronous Bloom filter based payload matching and look up/decision tree based packet classification with clock gating are proposed to reduce the switching power dissipations in the existing designs. Also, this paper proposes a new crossbar switch based packet classification and 2-to-1 multiplexer based buffered crossbar backplane to achieve high performance. Our proposed crossbar switch avoids the tri-state buffer based cross points due to their contention and power issues in the larger circuits. All these existing and proposed designs are implemented with 45nm CMOS technology. The synthesis results show that the proposed designs achieve significant improvement in power reduction over the existing designs. The proposed asynchronous Bloom filter based payload match architecture achieves 94.9% of reduction in PDP over Cuckoo design [5]. Similarly, the proposed 4×4 crossbar switch design achieves 57.8% of reduction in PDP than the existing buffered design [17].

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.

Performance-power consumption tradeoff in wearable epilepsy monitoring systems.

Automated seizure detection methods can be used to reduce time and costs associated with analyzing large volumes of ambulatory EEG recordings. These methods however have to rely on very complex, power hungry algorithms, implemented on the system backend, in order to achieve acceptable levels of accuracy. In size, and therefore power-constrained EEG systems, an alternative approach to the problem of data reduction is online data selection, in which simpler algorithms select potential epileptiform activity for discontinuous recording but accurate analysis is still left to a medical practitioner. Such a diagnostic decision support system would still provide doctors with information relevant for diagnosis while reducing the time taken to analyze the EEG. For wearable systems with limited power budgets, data selection algorithm must be of sufficiently low complexity in order to reduce the amount of data transmitted and the overall power consumption. In this paper, we present a low-power hardware implementation of an online epileptic seizure data selection algorithm with encryption and data transmission and demonstrate the tradeoffs between its accuracy and the overall system power consumption. We demonstrate that overall power savings by data selection can be achieved by transmitting less than 40% of the data. We also show a 29% power reduction when selecting and transmitting 94% of all seizure events and only 10% of background EEG.

Feature extraction using extrema sampling of discrete derivatives for spike sorting in implantable upper-limb neural prostheses.

Next generation neural interfaces for upper-limb (and other) prostheses aim to develop implantable interfaces for one or more nerves, each interface having many neural signal channels that work reliably in the stump without harming the nerves. To achieve real-time multi-channel processing it is important to integrate spike sorting on-chip to overcome limitations in transmission bandwidth. This requires computationally efficient algorithms for feature extraction and clustering suitable for low-power hardware implementation. This paper describes a new feature extraction method for real-time spike sorting based on extrema analysis (namely positive peaks and negative peaks) of spike shapes and their discrete derivatives at different frequency bands. Employing simulation across different datasets, the accuracy and computational complexity of the proposed method are assessed and compared with other methods. The average classification accuracy of the proposed method in conjunction with online sorting (O-Sort) is 91.6%, outperforming all the other methods tested with the O-Sort clustering algorithm. The proposed method offers a better tradeoff between classification error and computational complexity, making it a particularly strong choice for on-chip spike sorting.

High Performance and Low Power Hardware Implementation for Cryptographic Hash Functions

Since hash functions are cryptography's most widely used primitives, efficient hardware implementation of hash functions is of critical importance. The proposed high performance hardware implementation of the hash functions used sponge construction which generates desired length digest, considering two key design metrics: throughput and power consumption. Firstly, this paper introduces unfolding transformation which increases the throughput of hash function and pipelining and parallelism design techniques which reduce the delay. Secondly, we propose a frequency trade-off technique which can give us a scope of frequency value for making a trade-off between low dynamic power consumption and high throughput. Finally, we use load-enable based clock gating scheme to eliminate wasted toggle rate of signals in the idle mode of hash encryption system. We demonstrated the proposed design techniques by using 45 nm CMOS technology at 10 MHz. The results show that we can achieve up to 47.97 times higher throughput, 6.31% delay reduction, and 13.65% dynamic power reduction.

Feature extraction using first and second derivative extrema (FSDE) for real-time and hardware-efficient spike sorting

Next generation neural interfaces aspire to achieve real-time multi-channel systems by integrating spike sorting on chip to overcome limitations in communication channel capacity. The feasibility of this approach relies on developing highly efficient algorithms for feature extraction and clustering with the potential of low-power hardware implementation. We are proposing a feature extraction method, not requiring any calibration, based on first and second derivative features of the spike waveform. The accuracy and computational complexity of the proposed method are quantified and compared against commonly used feature extraction methods, through simulation across four datasets (with different single units) at multiple noise levels (ranging from 5 to 20% of the signal amplitude). The average classification error is shown to be below 7% with a computational complexity of 2N−3, where N is the number of sample points of each spike. Overall, this method presents a good trade-off between accuracy and computational complexity and is thus particularly well-suited for hardware-efficient implementation.

Power Efficient Sum of Absolute Difference Algorithms for video Compression

Video Compression (VC) is one of the resource hungry key element in video communication and is commonly achieved using Motion Estimation (ME). In this paper we proposed power efficient one bit full adder and one of the simple and easy metric called Sum of Absolute Difference (SAD) for estimating the motion vectors in motion estimation. SAD is primarily used to detect motion in the video sub system. Here we proposed power efficient 4X4 and 8X8 SAD architectures. The proposed 4X4 SAD proves that 29%, 63.23% and 61.31% improvement in leakage power, dynamic power and total power respectively as compared with existing 4X4 SAD. Similarly the proposed 8X8 SAD which proves that 57%, 46.16% and 46.78% improvement in Leakage Power (LP), Dynamic Power (DP) and Total Power (TP) respectively as compared with that of existing 8X8 SAD at the gate level. The designs are implemented in ASIC methodology using cadence tools. Keywords - SAD, ME, VC, CSA, DSP, LP, DP, TP, FPGA etc. I. INTRODUCTION Many recent multimedia applications of digital video systems such as video conferencing, video-on- demand, video-phone, distance learning and digital TV, object tracking and many more have become popular products because of their convenience. Such applications require video compression with ever higher compression ratios, better visual quality and high bandwidth. The high efficiency video compression commonly uses the efficient hardware architectures. In general the development of hardware architectures are designed to form the integrated circuits which allows parallel processing of data from various sub blocks of the architectures, however hardware architectures suffers from limitations such as algorithm flexibility due to timing dependencies, which arises from the dataflow of various blocks of the architecture. Thus the development of good architecture of video codec in integrated circuits is very important. The customization of video codec is the video compression in the modern state of the art real time Digital Signal Processing (DSP) systems. Video compression is one of the techniques in video processing system to reduce resource usage. The two primary challenges addressed during video compression are:  Limited Network bandwidth.  Limited Storage capacity. Hence the two important metrics of a video encoder are low computational complexity & low power hardware implementation. Present day world, compression ratio plays the major role in the field of video processing. The motion in the video scene will reduce the efficiency of the compression ratio. Hence the motion estimation field has seen the highest research topic and interested issue in the past a few decades. In short the motion estimation means the estimation of the displacement (or velocity) of image structures from one frame to another in a time sequence of 2-D images of the video in order to achieve video compression in video coding. The efficiency of the compression ratio can be increased by exploiting the similarities between the video frames. The simple metric system is the SAD algorithm, where the absolute differences between the corresponding elements are added up. There are varieties of video coding standards in the video processing systems; the modern video coding standard is H.264/AVC. This coding standard uses the Variable Block Size Motion Estimation (VBSME), in this standard; the computation requirements are much higher than the previous coding standards such as H.263/ MPEG-IV. In H.264/AVC, each picture frame is divided into many macro blocks.

Using a hybrid neuron in physiologically inspired models of the basal ganglia

Our current understanding of the basal ganglia (BG) has facilitated the creation of computational models that have contributed novel theories, explored new functional anatomy and demonstrated results complementing physiological experiments. However, the utility of these models extends beyond these applications. Particularly in neuromorphic engineering, where the basal ganglia's role in computation is important for applications such as power efficient autonomous agents and model-based control strategies. The neurons used in existing computational models of the BG, however, are not amenable for many low-power hardware implementations. Motivated by a need for more hardware accessible networks, we replicate four published models of the BG, spanning single neuron and small networks, replacing the more computationally expensive neuron models with an Izhikevich hybrid neuron. This begins with a network modeling action-selection, where the basal activity levels and the ability to appropriately select the most salient input is reproduced. A Parkinson's disease model is then explored under normal conditions, Parkinsonian conditions and during subthalamic nucleus deep brain stimulation (DBS). The resulting network is capable of replicating the loss of thalamic relay capabilities in the Parkinsonian state and its return under DBS. This is also demonstrated using a network capable of action-selection. Finally, a study of correlation transfer under different patterns of Parkinsonian activity is presented. These networks successfully captured the significant results of the originals studies. This not only creates a foundation for neuromorphic hardware implementations but may also support the development of large-scale biophysical models. The former potentially providing a way of improving the efficacy of DBS and the latter allowing for the efficient simulation of larger more comprehensive networks.