Low power hardware implementations for network packet processing elements

Abstract

The real world network packet processing demands high performance hardware to achieve the required speed. This paper proposes the various hardware optimizations on payload matching, packet classification, and backplane switch interconnects by allowing architectural changes in the existing designs. Here, asynchronous Bloom filter based payload matching and look up/decision tree based packet classification with clock gating are proposed to reduce the switching power dissipations in the existing designs. Also, this paper proposes a new crossbar switch based packet classification and 2-to-1 multiplexer based buffered crossbar backplane to achieve high performance. Our proposed crossbar switch avoids the tri-state buffer based cross points due to their contention and power issues in the larger circuits. All these existing and proposed designs are implemented with 45nm CMOS technology. The synthesis results show that the proposed designs achieve significant improvement in power reduction over the existing designs. The proposed asynchronous Bloom filter based payload match architecture achieves 94.9% of reduction in PDP over Cuckoo design [5]. Similarly, the proposed 4×4 crossbar switch design achieves 57.8% of reduction in PDP than the existing buffered design [17].