Clock gating aware energy efficient Frame buffer design on FPGA

Abstract

In this work, clock gating technique is applied on the Frame Buffers in order to get more energy efficient Frame Buffers. Frame Buffer is an in-built memory of digital Image Processor, which is writeable by the CPU and readable by the Video Interface and used to store color of each pixel. Clock gating is a power saving technique which turns off the inactive component of design in order to save power consumption. When frame buffer is operating on 10 GHz speed, 98.41% reduction in clock power and 2.51% reduction in I/O power is possible with clock gating. The main purpose of frame buffer is to store or access images more rapidly usually at video rates. Therefore, highest speed of 1THz is applied for frame buffer and we get 98.28% reduction in clock power and 96.58% reduction in I/O power. In that way, we achieve our design goal of both high performance (in range of 1THz) and energy efficient (in range of 90% reduction in power) frame buffer design to achieve high performance energy efficient digital image processor (HPEEC-DIP). In this experiment, Xilinx 14.6 is used as simulator, Verilog is used as verification language, XPower is a power consumption estimator, Frame Buffer is target design and Virtex-6 is targeting 40nm FPGA Device.