Low-power Decoder Research Articles

Spiking Neural Network Equalizer With Fast and Low Power Decoding for IM/DD Optical Communication

Spiking Neural Network Equalizer With Fast and Low Power Decoding for IM/DD Optical Communication

High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL) in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the mixed-logic circuit, new n-Transistor (T) NAND/AND structures were provided for decoders, while achieving fewer transistors, faster speed, lower power dissipation as compared to traditional circuits, and having full-swing capability and good noise immunity. Experiments were conducted using TSMC 28 nm process for mixed-logic decoders, and the results show the superiority in terms of propagation delay and power dissipation, compared to the conventional corresponding circuits. A mixed-logic 2-4 decoder exhibits 36 % reduction in propagation delay and 10 % improvement in power dissipation; A mixed-logic 3-8 decoder exhibits 27 % reduction in propagation delay and 5.5 % improvement in power dissipation; While, A mixed-logic 4-16 decoder exhibits 30 % reduction in propagation delay and 5 % improvement in power dissipation; As well, A mixed-logic 5-32 decoder exhibits 34 % reduction in propagation delay and 6.3 % improvement in power dissipation.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder's potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

Demonstrating the Viability of Mapping Deep Learning Based EEG Decoders to Spiking Networks on Low-powered Neuromorphic Chips.

Accurate and low-power decoding of brain signals such as electroencephalography (EEG) is key to constructing brain-computer interface (BCI) based wearable devices. While deep learning approaches have progressed substantially in terms of decoding accuracy, their power consumption is relatively high for mobile applications. Neuromorphic hardware arises as a promising solution to tackle this problem since it can run massive spiking neural networks with energy consumption orders of magnitude lower than traditional hardware. Herein, we show the viability of directly mapping a continuous-valued convolutional neural network for motor imagery EEG classification to a spiking neural network. The converted network, able to run on the SpiNNaker neuromorphic chip, only shows a 1.91% decrease in accuracy after conversion. Thus, we take full advantage of the benefits of both deep learning accuracies and low-power neuro-inspired hardware, properties that are key for the development of wearable BCI devices.

Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation

Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation

AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

Realizing a Low-Power Head-Mounted Phase-Only Holographic Display by Light-Weight Compression.

Head-mounted holographic displays (HMHD) are projected to be the first commercial realization of holographic video display systems. HMHDs use liquid crystal on silicon (LCoS) spatial light modulators (SLM), which are best suited to display phase-only holograms (POH). The performance/watt requirement of a monochrome, 60 fps Full HD, 2-eye, POH HMHD system is about 10 TFLOPS/W, which is orders of magnitude higher than that is achievable by commercially available mobile processors. To mitigate this compute power constraint, display-ready POHs shall be generated on a nearby server and sent to the HMHD in compressed form over a wireless link. This paper discusses design of a feasible HMHD-based augmented reality system, focusing on compression requirements and per-pixel rate-distortion trade-off for transmission of display-ready POH from the server to HMHD. Since the decoder in the HMHD needs to operate on low power, only coding methods that have low-power decoder implementation are considered. Effects of 2D phase unwrapping and flat quantization on compression performance are also reported. We next propose a versatile PCM-POH codec with progressive quantization that can adapt to SLM-dynamic-range and available bitrate, and features per-pixel rate-distortion control to achieve acceptable POH quality at target rates of 60-200 Mbit/s that can be reliably achieved by current wireless technologies. Our results demonstrate feasibility of realizing a low-power, quality-ensured, multi-user, interactive HMHD augmented reality system with commercially available components using the proposed adaptive compression of display-ready POH with light-weight decoding.

Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard

This paper presents the design and implementation of ultrawideband digital baseband transceiver for wireless body area networks (WBAN) applications. The power dissipation and area of the proposed architecture are minimized by combining algorithmic and architectural level modifications. A new algorithm for Bose–Chaudhuri–Hocquenghem (BCH) encoding is implemented and the coding gain of the BCH decoder is improved by 0.5 dB, with a cost of only one percent area overhead. An area efficient, low-complexity, and low-power BCH decoder is implemented and it has 42 $\%$ lower area and 38 $\%$ lower power dissipation compared to a conventional hard-decision decoder. Other salient features of this paper include a low-complexity, low-power packet detection unit, and a low-power module for removing the shortening bits. The baseband transceiver has been designed in 90 nm CMOS technology and it has an energy efficiency of 73 pJ/bit in transmitter mode and 225 pJ/bit in receiver mode.

A New Approach for Low Power Decoder for Memory Array

SRAMs are important building blocks in many digital applications, such as microprocessors and cache memories. Decoders are the significant components in SRAMs. Address decoder is vital part of SRAM memory. Choice of capacity cell and read operation is relies on upon decoder. Henceforth, execution of SRAM is relies on upon these parts. This work studies the location decoder for SRAM memory, focusing on deferral streamlining and control effective circuit systems. We have focused on ideal decoder structure with slightest number of transistors to diminish range of SRAM. Usually, in Memory Chip, it consumes almost fifty percent of the total chip access time and power. Parameters which has to be considered while designing an address decoders are, first appropriate circuit technique has to be chosen and the second thing is sizing constrains of the transistors. Modified hybrid type of decoding topology is illustrated and it is compared with traditional type decoders which include both static and dynamic types using 180 nm CMOS technology in Cadence Virtuoso environment.

Iteration-Aware LDPC Code Design for Low-Power Optical Communications

Recent low-density parity-check (LDPC) codes have shown capacity-approaching performance for various communications systems. However, their promising performance cannot always be obtained due to practical constraints, such as finite codeword length, finite iteration, finite memory, and finite precision. In this paper, we focus on a practical design method of high-performance LDPC codes under a constraint of finite-iteration decoding for low-power optical communications. We introduce an iteration-aware LDPC code design approach, which is based on decoding trajectory in extrinsic information transfer chart analysis. It is demonstrated that an LDPC code designed by the conventional curve-fitting method exhibits nearly 2 dB of penalty, when the maximum number of iterations is limited. The results suggest that the LDPC code should be adaptively changed, e.g., when the number of decoding iterations is decreased to save power consumption. We also extend our design method to a multi-objective optimization concept by taking average degrees into account, so that the threshold and the computational complexity are minimized at the same time. The proposed Pareto-optimal codes can achieve additional 2-dB gain or 50% complexity reduction at maximum, in low-power decoding scenarios.

Compact, High Speed and Low power Decoders for Future Generation System Building

system building has become highly competitive from the point of reducing area, power and increasing the speed. To address these issues, many technologies are being tried. Quantum Dot Cellular Automation is one such technology. This technology is in its infant state as far as its physical implementation and verification are concerned. However the researchers have come out with theoretical models and proposed many compact, fast and low power dissipating digital blocks. Decoders are one of the standard combinational modules used as the basic building blocks for efficient digital system design. Here in this paper we implement decoders in QCA using different techniques and analyze them with respect to area, time and energy. From the implementation and simulation results obtained using QCADESIGNER version 2.0.3 we have observed that, the 2:4 decoders implemented with and without the enable input using both single layer and multilayer techniques utilize minimum area, time and energy. KeywordsDot Cellular Automata (QCA), Decoder, Coincident

Trellis-Based QC-LDPC Convolutional Codes Enabling Low Power Decoders

In this paper, we propose a new type of code called Trellis-based Quasi-Cyclic (TQC)-LDPC convolutional code, which is a special case of protograph-based LDPC convolutional codes. The proposed TQC-LDPC convolutional code can be derived from any QC-LDPC block code by introducing trellis-based convolutional dependency to the code. The main advantage of the proposed TQC-LDPC convolutional code is that it allows reduced decoder complexity and input granularity (which is defined as the minimum number of input information bits the code requires to generate a codeword) while maintaining the same bit error-rate as the underlying QC-LDPC block code ensemble. We also propose two related power-efficient encoding methods to increase the code rate of the derived TQC-LDPC convolutional code. The newly derived short constraint length TQC-LDPC convolutional codes enable low complexity trellis-based decoders and one such decoder is proposed and described in this paper (namely, QC-Viterbi). The TQC-LDPC convolutional codes and the QC-Viterbi decoder are compared to conventional LDPC codes and Belief Propagation (BP) iterative decoders with respect to bit-error-rate (BER), signal-to-noise ratio (SNR), and decoder complexity. We show both numerically and through hardware implementation results that the proposed QC-Viterbi decoder outperforms the BP iterative decoders by at least 1 dB for same complexity and BER. Alternatively, the proposed QC-Viterbi decoder has 3 times lower complexity than the BP iterative decoder for the same SNR and BER. This low decoding complexity, low BER, and fine granularity makes it feasible for the proposed TQC-LDPC convolutional codes and associated trellis-based decoders to be efficiently implemented in high data rate, next generation mobile systems.

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

Low Power Decoding of LDPC Codes

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems

This article presents a low-power decoder design for joint source-channel decoding (JSCD) based on a novel unequal error protection (UEP) scheme over additive white gaussian noise (AWGN) channels. Conventional JSCD schemes, adopting low-density parity check (LDPC) codes for multimedia devices, typically operate at a fixed-time decoding loop, regardless of the quality of data received. We present a JSCD scheme that achieves reduction in power through minimum energy decoding and dynamic voltage and frequency scaling (DVFS). Consequently, up to 39% power reduction is achieved in Foreman, Akiyo, and Mobile video streams without performance degradation in reconstructed video quality.

Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture

This paper presents a low-power design scheme to lower baseband energy consumption using joint source decoding and dynamic voltage and frequency scaling (DVFS). This scheme combines unequal error protection (UEP) developed for error resilient video coding with a variable iteration low density parity check (LDPC) decoder to trade off performance against energy consumption. Using the proposed method, we determine LDPC decoding configurations that achieve minimum energy consumption while satisfying pre-specified image quality at the receiver. The implementation results yield 17%, 37%, 52% power reductions with 0, 0.3, 1.1 dB peak signal to noise ratio (PSNR) degradation at 3.6 dB SNR in Foreman test stream respectively.

A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing for Wireless Applications

This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity. Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

Embedded Digital Signal Processing Systems

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.

Low-power log-MAP decoding based on reduced metric memory access

Due to the powerful error correcting performance, turbo codes have been adopted in many wireless communication standards such as W-CDMA and CDMA2000. Although several low-power techniques have been proposed, power consumption is still a major issue to be solved in practical implementations. Since turbo decoding is classified as a memory-intensive algorithm, reducing memory accesses is crucial to achieve a low power design. To reduce the number of memory accesses for maximum a posteriori (MAP) decoding, this paper proposes an approximate reverse calculation method that can be implemented with simple arithmetic operations such as addition and comparison. Simulation results show that the proposed method applied to the W-CDMA standard reduces the access rate of the backward metric memory by 87% without degrading error-correcting performance. A prototype log-MAP decoder based on the proposed reverse calculation achieves 29% power reduction compared to a conventional decoder that does not use the reverse calculation