LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Tinoosh Mohsenin,Bevan M Baas,Houshmand Shirani-Mehr

doi:10.1155/2013/913018

Abstract

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

Highlights

Communication systems are becoming a standard requirement of every computing platform from wireless sensors, mobile telephony, netbooks, and server class computers
2 has the least hardware increase, which has a 5% increase in check node processor and variable node processor area compared to Split-Row Threshold
1 has the largest hardware overhead due to the added muxes and gates for saturation implementation with a 15% increase in check node processor area and a 6% increase in variable node processor area compared to the original design

Summary

Introduction

Communication systems are becoming a standard requirement of every computing platform from wireless sensors, mobile telephony, netbooks, and server class computers. Local and cellular wireless communication throughputs are expected to increase to hundreds of Mbps and even beyond 1 Gbps [1,2,3]. With this increased growth for bandwidth comes larger systems integration complexity and higher energy consumption per packet. Common iterative decoding algorithms are Sum-Product Algorithm (SPA) [19] and MinSum algorithms [20]. Both algorithms are defined by a check node update equation that generates α and a variable node update equation that generates β.

Methods

Results

Conclusion