Low Computational Power Research Articles

Intelligent vehicle localization and navigation based on intersection fingerprint roadmap (IRM) in underground parking lots

The localization and navigation of underground parking lots presents a ‘last mile’ problem for intelligent vehicles. To address the issues of poor localization and navigation efficiency caused by the lack of global navigation satellite system signals in this scenario, this study presents a low-cost and computationally efficient real-time localization and navigation algorithm. The algorithm begins by constructing a node fingerprint based on the characteristics of underground parking lot intersections and proposes an intersection fingerprint roadmap (IRM). To address the problem of difficult initial position computation during navigation, a node-level localization method based on scene matching and pose calculation is proposed and then combined with the IRM. Finally, the IRM is used to search for routes on the scene plan and perform path smoothing to obtain a globally feasible driving route. The algorithm proposed in this study can achieve fast vehicle localization and real-time navigation with low computational power, and the proposed localization method can be applied not only to underground parking lots but also to other outdoor scenes. The method is evaluated on datasets collected from different environments, and the experimental results show that the algorithm has an average localization error of approximately 20 cm and provides faster navigation speed and smoother navigation in comparison with other algorithms.

Computation via Neuron-like Spiking in Percolating Networks of Nanoparticles.

The biological brain is a highly efficient computational system in which information processing is performed via electrical spikes. Neuromorphic computing systems that work on similar principles could support the development of the next generation of artificial intelligence and, in particular, enable low-power edge computing. Percolating networks of nanoparticles (PNNs) have previously been shown to exhibit critical spiking behavior, with promise for highly efficient natural computation. Here we employ a rate coding scheme to show that PNNs can perform Boolean operations and image classification. Near perfect accuracy is achieved in both tasks by manipulating the spiking activity using certain control voltages. We demonstrate that the key to successful computation is that nanoscale tunnel gaps within the percolating networks transform input data through a powerful modulus-like nonlinearity. These results provide a basis for implementation of further computational schemes that exploit the brain-like criticality of these networks.

Optical Vivaldi Antenna Array for Solar Energy Harvesting

In this paper, we try to find the best solution for our energy harvesting application by designing an efficient optical antenna which receives the solar radiation and converts it from AC to DC by integrating a rectifier. This work consists of designing a Vivaldi optical antenna with a maximum electric field captured in its gap. We also examine the use the optical array(double, four and eight) in order to increase the captured electric field concentrated in the common gap, compared to the single structure . Feeding lines are used to ride the captured electric field from the gap of each single antenna to a common gap. These innovative systems are small electronic devices often consisting of a low-power computer, wireless sensors, an antenna and capable of communicate with their environment. These devices also have an on-board energy source in the form of cells or batteries that require maintenance operations. periodic replacement or recharging, which can hinder the mobility and deployment of these communicating systems for the greatest number. This is the reason why we Today, we also note the very strong interest in improving energy autonomy and even the complete independence of these systems with respect to on-board sources.

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS

This brief presents a gradient-based maximum eye tracking (GMET) scheme employed in the forwarded-clock receiver, including baud-rate clock and data recovery (CDR) and 2-tap adaptive decision feedback equalization (DFE). By optimizing the widely used gradient ascent method for robust operation, GMET achieves low computational power and high stability. Also, simultaneous adaptation using the unified algorithm enables low power consumption and low design complexity. Compared with the previous baud-rate CDR, superior performance is demonstrated under high-loss conditions. The prototype receiver is fabricated in 28-nm CMOS and occupies an active area of 0.106 mm2. At the data rate of 28 Gb/s, the receiver consumes 47 mW, corresponding to an energy efficiency of 1.68 pJ/b. Furthermore, with a channel loss of 27.7 dB at the Nyquist frequency, joint operation of the CDR and the DFE adaptation offers measured results with a margin of 0.17 unit interval (UI) at a BER lower than 10-12.

Cooperative Computing Offloading Scheme via Artificial Neural Networks for Underwater Sensor Networks

Aiming at the problem of being unable to meet some high computing power, high-precision applications due to the limited capacity of underwater sensor nodes, and the difficulty of low computation power, in this paper, we introduce the edge servers, known as base stations for underwater sensor nodes, and propose a scheme to process the computational tasks based on coalition game theory. This scheme provides functions such as cooperation among different base stations within the coalition, the smart division of tasks, and efficient computational offloading. In order to reduce the complexity of the algorithm, the artificial neural network model is introduced into the method. Each task is divided into sub-parts and fed to an artificial neural network for training, testing, and validation. In addition, the scheme delivers the computed task from base stations back to sink nodes via a shortened path to enhance the service reliability. Due to the mobility of the base station in the ocean, our proposed scheme takes into account the dynamic environment at the same time. The simulation results show that, compared with the existing state-of-the-art methods, the success rate of our proposed approach improves by 30% compared with the Greedy method. The total service time of our proposed approach decreases by 12.6% compared with the Greedy method and 31.2% compared with the Always-Migrate method.

Superlow Power Consumption Memristor Based on Borphyrin-Deoxyribonucleic Acid Composite Films as Artificial Synapse for Neuromorphic Computing.

Memristor synapses based on green and pollution-free organic materials are expected to facilitate biorealistic neuromorphic computing and to be an important step toward the next generation of green electronics. Metalloporphyrin is an organic compound that widely exists in nature with good biocompatibility and stable chemical properties, and has already been used to fabricate memristors. However, the application of metalloporphyrin-based memristors as synaptic devices still faces challenges, such as realizing a high switching ratio, low power consumption, and bidirectional conductance modulation. We developed a memristor that improves the resistive switching (RS) characteristics of Zn(II)meso-tetra(4-carboxyphenyl) porphine (ZnTCPP) by combining it with deoxyribonucleic acid (DNA) in a composite film. The as-fabricated ZnTCPP-DNA-based device showed excellent RS memory characteristics with a sufficiently high switching ratio of up to ∼104, super low power consumption of ∼39.56 nW, good cycling stability, and data retention capability. Moreover, bidirectional conductance modulation of the ZnTCPP-DNA-based device can be controlled by modulating the amplitudes, durations, and intervals of positive and negative pulses. The ZnTCPP-DNA-based device was used to successfully simulate a series of synaptic functions including long-term potentiation, long-term depression, spike time-dependent plasticity, paired-pulse facilitation, excitatory postsynaptic current, and human learning behavior, which demonstrates its potential applicability to neuromorphic devices. A two-layer artificial neural network was used to demonstrate the digit recognition ability of the ZnTCPP-DNA-based device, which reached 97.22% after 100 training iterations. These results create a new avenue for the research and development of green electronics and have major implications for green low-power neuromorphic computing in the future.

Human emotion recognition with a microcomb-enabled integrated optical neural network

Abstract State-of-the-art deep learning models can converse and interact with humans by understanding their emotions, but the exponential increase in model parameters has triggered an unprecedented demand for fast and low-power computing. Here, we propose a microcomb-enabled integrated optical neural network (MIONN) to perform the intelligent task of human emotion recognition at the speed of light and with low power consumption. Large-scale tensor data can be independently encoded in dozens of frequency channels generated by the on-chip microcomb and computed in parallel when flowing through the microring weight bank. To validate the proposed MIONN, we fabricated proof-of-concept chips and a prototype photonic-electronic artificial intelligence (AI) computing engine with a potential throughput up to 51.2 TOPS (tera-operations per second). We developed automatic feedback control procedures to ensure the stability and 8 bits weighting precision of the MIONN. The MIONN has successfully recognized six basic human emotions, and achieved 78.5 % accuracy on the blind test set. The proposed MIONN provides a high-speed and energy-efficient neuromorphic computing hardware for deep learning models with emotional interaction capabilities.

A Unified Parallel CORDIC-Based Hardware Architecture for LSTM Network Acceleration

Deep Neural Networks (DNNs) have recently become the standard tool for solving various practical problems in a wide range of applications with state-of-the-art performance. Recurrent Neural Networks (RNNs) such as Long Short-Term Memory (LSTM) are a subset of DNNs with fully connected single or multi-layer networks. The complex neurons and internal states of LSTM networks enable them to build a memory of events, making them ideal for time series applications. Despite the great potential of LSTM networks, their heterogeneous operations and computational resource requirements create a vast gap when it comes to the fast processing time required in real-time applications using low-power, low-cost edge devices. This work proposes a novel hardware architecture that combines serial-parallel computation with matrix algebra concepts and efficient low-power computer arithmetics for LSTM network acceleration. The hardware is based on a systolic ring of outer-product-based processing elements (PEs) and a reusable single activation function block (AFB). PEs and AFB are implemented using the coordinate rotation digital computer algorithm (CORDIC) in the linear and hyperbolic modes. Unlike most approaches, the proposed hardware can be configured to perform recurrent and non-recurrent fully connected layers (FC) computations, making it suitable for various low-power edge applications. The architecture is validated on the Xilinx PYNQ-Z1 development board using an open-source time series dataset. The implemented design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$114 \mu s$</tex-math></inline-formula> average latency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1.8GOPS$</tex-math></inline-formula> throughput. The proposed design's low latency and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$0.438W$</tex-math></inline-formula> power consumption makes it suitable for resource-constrained edge platforms.

Evaluation of Blockchain Networks’ Scalability Limitations in Low-Powered Internet of Things (IoT) Sensor Networks

With the development of Internet of Things (IoT) technologies, industries such as healthcare have started using low-powered sensor-based devices. Because IoT devices are typically low-powered, they are susceptible to cyber intrusions. As an emerging information security solution, blockchain technology has considerable potential for protecting low-powered IoT end devices. Blockchain technology provides promising security features such as cryptography, hash functions, time stamps, and a distributed ledger function. Therefore, blockchain technology can be a robust security technology for securing IoT low-powered devices. However, the integration of blockchain and IoT technologies raises a number of research questions. Scalability is one of the most significant. Blockchain’ scalability of low-powered sensor networks needs to be evaluated to identify the practical application of both technologies in low-powered sensor networks. In this paper, we analyse the scalability limitations of three commonly used blockchain algorithms running on low-powered single-board computers communicating in a wireless sensor network. We assess the scalability limitations of three blockchain networks as we increase the number of nodes. Our analysis shows considerable scalability variations between three blockchain networks. The results indicate that some blockchain networks can have over 800 ms network latency and some blockchain networks may use a bandwidth over 1600 Kbps. This work will contribute to developing efficient blockchain-based IoT sensor networks.

Energy Efficient Compressor Cell for Low Power Computing

As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.

Synergy of Patent and Open-Source-Driven Sustainable Climate Governance under Green AI: A Case Study of TinyML

Green AI (Artificial Intelligence) and digitalization facilitate the “Dual-Carbon” goal of low-carbon, high-quality economic development. Green AI is moving from “cloud” to “edge” devices like TinyML, which supports devices from cameras to wearables, offering low-power IoT computing. This study attempts to provide a conceptual update of climate and environmental policy in open synergy with proprietary and open-source TinyML technology, and to provide an industry collaborative and policy perspective on the issue, through using differential game models. The results show that patent and open source, as two types of TinyML innovation, can benefit a wide range of low-carbon industries and climate policy coordination. From the case of TinyML, we find that collaboration and sharing can lead to the implementation of green AI, reducing energy consumption and carbon emissions, and helping to fight climate change and protect the environment.

Efficient human activity recognition with spatio-temporal spiking neural networks.

In this study, we explore Human Activity Recognition (HAR), a task that aims to predict individuals' daily activities utilizing time series data obtained from wearable sensors for health-related applications. Although recent research has predominantly employed end-to-end Artificial Neural Networks (ANNs) for feature extraction and classification in HAR, these approaches impose a substantial computational load on wearable devices and exhibit limitations in temporal feature extraction due to their activation functions. To address these challenges, we propose the application of Spiking Neural Networks (SNNs), an architecture inspired by the characteristics of biological neurons, to HAR tasks. SNNs accumulate input activation as presynaptic potential charges and generate a binary spike upon surpassing a predetermined threshold. This unique property facilitates spatio-temporal feature extraction and confers the advantage of low-power computation attributable to binary spikes. We conduct rigorous experiments on three distinct HAR datasets using SNNs, demonstrating that our approach attains competitive or superior performance relative to ANNs, while concurrently reducing energy consumption by up to 94%.

Exploring Trade-Offs in Spiking Neural Networks.

Spiking neural networks (SNNs) have emerged as a promising alternative to traditional deep neural networks for low-power computing. However, the effectiveness of SNNs is not solely determined by their performance but also by their energy consumption, prediction speed, and robustness to noise. The recent method Fast & Deep, along with others, achieves fast and energy-efficient computation by constraining neurons to fire at most once. Known as time-to-first-spike (TTFS), this constraint, however, restricts the capabilities of SNNs in many aspects. In this work, we explore the relationships of performance, energy consumption, speed, and stability when using this constraint. More precisely, we highlight the existence of trade-offs where performance and robustness are gained at the cost of sparsity and prediction latency. To improve these trade-offs, we propose a relaxed version of Fast & Deep that allows for multiple spikes per neuron. Our experiments show that relaxing the spike constraint provides higher performance while also benefiting from faster convergence, similar sparsity, comparable prediction latency, and better robustness to noise compared to TTFS SNNs. By highlighting the limitations of TTFS and demonstrating the advantages of unconstrained SNNs, we provide valuable insight for the development of effective learning strategies for neuromorphic computing.

Supervised learning and pattern recognition in photonic spiking neural networks based on MRR and phase-change materials

Traditional computers are limited by the separation of memory and processor units, is difficult to achieve fast, efficient, and low-power computing. While photonic spiking neural networks (SNNs) can overcome these shortcomings, they encounter limitations in large-scale integration. Silicon photonics platform, compatible with mature Complementary Metal Oxide Semiconductor (CMOS) platforms, is a promising candidate for realizing large-scale photonic SNNs. In this work, we proposed an integrated photonic SNN by exploiting the photonic properties of phase-change material (PCM) Ge2Sb2Te5 (GST) and micro-ring resonators (MRR), and demonstrated its integrate-and-fire (IF) behavior. Based on a system-level behavioral model, we adopt an improved Tempotron-like ReSuMe supervised learning algorithm to train the proposed photonic SNNs and complete a pattern recognition task for the clock's 12 clockwise directions. Then the influence of different noise levels is considered, and the accuracy is close to 1 when the noise level is less than 0.2. We propose a photonic implementation of such an SNN system, and use wavelength division multiplexing to achieve a scalable architecture for the pattern recognition task. The collaborative design and optimization of hardware architecture and algorithm are realized, providing a theoretical basis for the realization of photonic SNN based on MRRs and PCM.

Feature independent Filter Pruning by Successive Layers analysis

Convolutional neural networks (CNNs) have become deeper and wider over time. However due to low computational power, mobile devices or embedded systems cannot use very deep models. Filter pruning solves this by eliminating redundant filters. Pruning can be performed in a feature dependent or independent manner. Feature dependent methods require extensive time to determine the filter importance as these methods require generation and processing of feature maps for each example. Additionally, in iterative pruning, filter importance is computed several times based on the current state. This increases algorithm execution time further. However, existing feature independent methods are fast, but they perform poor as they compute importance using only current layer filter weights. However, our analysis suggests that both the current and succeeding layer filters are crucial to determine filter importance. We propose ‘Filter Pruning by Successive Layers analysis’ (FPSL), a novel feature independent algorithm, that considers the effect of pruning a filter on the generation of feature maps for the first time. Moreover, FPSL does not require layer-wise retraining, rigorous hyperparameter search for fine-tuning, or human intervention to set the pruning percentage per layer. These make FPSL extremely fast, efficient, and adaptive. Thus it follows iterative pruning and retraining. FPSL outperforms the state-of-the-art (SOTA) methods on extensive experiments with different datasets (CIFAR, ImageNet) and architectures (VGG, ResNet, MobileNet). It decreases the computational burden of VGG16 by half but improves CIFAR10 and CIFAR100 accuracy. Even for ImageNet, FPSL reduces 42.7% floating point operations (FLOPs) while maintaining top-1 accuracy for ResNet50.

Enabling secure lightweight mobile Narrowband Internet of Things (NB-IoT) applications using blockchain

Narrowband Internet of Things (NB-IoT) is a low bandwidth 3GPP communication standard transmitting small quantities of data over long distances at random intervals. However, as NB-IoT cannot support seamless handover between base stations, its applications are limited to stationary devices, which may result in the potential risk of fake base station connections in an attempt to maintain connectivity across cells. Considering characteristics such as low power consumption and high connection density, researchers envision using NB-IoT in mobile applications such as public-bike sharing, pet tracking etc. Connecting NB-IoT devices using decentralised architecture such as blockchain ensures seamless communication in mobile applications and eliminates bottlenecks due to multiple data requests observed in centralised networks. In this paper, we develop a hybrid blockchain framework facilitating mutual authentication between base stations to enhance user privacy and prevent fake base station connections and certificate transfers. Zero-knowledge proof used as the consensus algorithm enhances user privacy and message confidentiality. IoT devices are designed to store the hashes of their approved transactions as a linear hash chain instead of the complete merkle tree to minimise hash verification complexity. Additionally, base station memory is partitioned dynamically to enhance scalability and memory utilisation efficiency. We prototype our framework on Remix IDE in Ethereum and implement it on Raspberry Pi 4. The security of the proposed framework is formally verified using Scyther. Further, we show that our approach achieves 80.50% lower computational power, 74.73% lower execution time and 50% lower memory, respectively, in comparison with existing schemes making our proposed scheme lightweight.

Experimental study and model development of bifacial photovoltaic power plants for Indian climatic zones

Bifacial photovoltaic technology is considered an emerging and promising PV technology. However, the unavailability of proven field data or efficient models prevents the stakeholders from going ahead with this technology. The currently available bifacial performance models have limitations; they are location specific, for a single bifacial PV module alone, or ground-level installed bifacial PV only. This paper develops an experimentally validated view factor-based optical model using the Cross-string rule to predict the power output and bifacial gain for bifacial PV power plants with good accuracy and low computation power and time. An optimal model for the best performance of bifacial PV at any location was also suggested by optimizing the parameters like the pitch, height of installations, and slope. The results show that the year-round performance of bifacial PV in cities in India's five climatic zones is 30.54%–34.93% higher than the monofiacial PV panels at an average ground albedo of 30%. Bi-annual tracking improved a bifacial PV's overall power output and bifacial gain. The financial indicators like Levelised cost of energy, Net present value, Discounted payback period, and Internal rate of return indicate higher financial gain from the bifacial PV power plant compared to monofacial PV power plant.

Evolution of Winning Solutions in the 2021 Low-Power Computer Vision Challenge

Evolution of Winning Solutions in the 2021 Low-Power Computer Vision Challenge

Combinatorial MAB-Based Joint Channel and Spreading Factor Selection for LoRa Devices.

Long-Range (LoRa) devices have been deployed in many Internet of Things (IoT) applications due to their ability to communicate over long distances with low power consumption. The scalability and communication performance of the LoRa systems are highly dependent on the spreading factor (SF) and channel allocations. In particular, it is important to set the SF appropriately according to the distance between the LoRa device and the gateway since the signal reception sensitivity and bit rate depend on the used SF, which are in a trade-off relationship. In addition, considering the surge in the number of LoRa devices recently, the scalability of LoRa systems is also greatly affected by the channels that the LoRa devices use for communications. It was demonstrated that the lightweight decentralized learning-based joint channel and SF-selection methods can make appropriate decisions with low computational complexity and power consumption in our previous study. However, the effect of the location situation of the LoRa devices on the communication performance in a practical larger-scale LoRa system has not been studied. Hence, to clarify the effect of the location situation of the LoRa devices on the communication performance in LoRa systems, in this paper, we implemented and evaluated the learning-based joint channel and SF-selection methods in a practical LoRa system. In the learning-based methods, the channel and SF are decided only based on the ACKnowledge information. The learning methods evaluated in this paper were the Tug of War dynamics, Upper Confidence Bound 1, and ϵ-greedy algorithms. Moreover, to consider the relevance of the channel and SF, we propose a combinational multi-armed bandit-based joint channel and SF-selection method. Compared with the independent methods, the combinations of the channel and SF are set as arms. Conversely, the SF and channel are set as independent arms in the independent methods that are evaluated in our previous work. From the experimental results, we can see the following points. First, the combinatorial methods can achieve a higher frame success rate and fairness than the independent methods. In addition, the FSR can be improved by joint channel and SF selection compared to SF selection only. Moreover, the channel and SF selection dependents on the location situation to a great extent.

Ultrathin SrTiO3-based oxide memristor with both drift and diffusive dynamics as versatile synaptic emulators for neuromorphic computing

Abstract Artificial synapses are electronic devices that simulate important functions of biological synapses, and therefore are the basic components of artificial neural morphological networks for brain-like computing. One of the most important objectives for developing artificial synapses is to simulate the characteristics of biological synapses as much as possible, especially their self-adaptive ability to external stimuli. Here, we have successfully developed an artificial synapse with multiple synaptic functions and highly adaptive characteristics based on a simple SrTiO3/Nb: SrTiO3 heterojunction type memristor. Diverse functions of synaptic learning, such as short-term/long-term plasticity (STP/LTP), transition from STP to LTP, learning–forgetting–relearning behaviors, associative learning and dynamic filtering, are all bio-realistically implemented in a single device. The remarkable synaptic performance is attributed to the fascinating inherent dynamics of oxygen vacancy drift and diffusion, which give rise to the coexistence of volatile- and nonvolatile-type resistive switching. This work reports a multi-functional synaptic emulator with advanced computing capability based on a simple heterostructure, showing great application potential for a compact and low-power neuromorphic computing system.