Low-power Circuit Research Articles

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Low-power and cost-effective readout circuit design for compact semiconductor gas sensor systems

This study introduces a novel readout circuit architecture that enhances semiconductor gas sensor systems by reducing power consumption, enabling miniaturization, and improving economic viability. Validated at the PCB level, the design shows strong commercial potential by addressing power efficiency and signal accuracy challenges. The technology is adaptable for applications in environmental monitoring, industrial safety, and medical diagnostics, where efficient and reliable gas sensing is essential.

Efficient quantum-dot adder optimisation and analysis for future circuits

ABSTRACT In recent years, the rapid scaling of transistors has necessitated the exploration of advanced alternatives to Complementary metal oxide semiconductor(CMOS) technology for future progress. Quantum-dot cellular automata(QCA) technology has emerged as a promising solution, offering highly dense, high-speed, and low-power circuits. Among the critical digital building blocks, adder circuits play a crucial role in arithmetic and logic units. Consequently, optimising these circuits in terms of area, delay, and quantum cost is essential for the development of efficient designs. This paper presents effective multi-layer n-bit ripple carry adder(RCA) circuits, utilising full adder(FA) circuit. The outputs are generated in distinct layers and verified using the QCADesigner-Ev2.2 tool with bi-stable and coherence vector energy setups, employing Euler and Runge-Kutta methods.Additionally, the proposed designs are evaluated for various design metrics at three different scale factors(1,0.8889,and 0.7778), corresponding to cell sizes of 18 × 18 nm , 16 × 16 nm , and 14 × 14 nm respectively. The temperature’s impact on the average output polarisation of the FA is explored. The research demonstrates an n-bit-RCA surpassing existing designs with cost optimisations of 89.5%, 86%, and 90.3% for 4-bit,8-bit and 16-bit circuits, respectively. The paper also provides a thorough energy dissipation analysis for the proposed adder design.

Fast scalable and low-power quantum circuit simulation on the cluster of GPUs platforms

Fast scalable and low-power quantum circuit simulation on the cluster of GPUs platforms

Realization of Extremely High-Gain and Low-Power in nMOS Inverter Based on Monolayer WS2 Transistor Operating in Subthreshold Regime.

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

Picosecond Femtojoule Resistive Switching in Nanoscale VO2 Memristors.

Beyond-Moore computing technologies are expected to provide a sustainable alternative to the von Neumann approach not only due to their down-scaling potential but also via exploiting device-level functional complexity at the lowest possible energy consumption. The dynamics of the Mott transition in correlated electron oxides, such as vanadium dioxide, has been identified as a rich and reliable source of such functional complexity. However, its full potential in high-speed and low-power operation has been largely unexplored. We fabricated nanoscale VO2 devices embedded in a broadband test circuit to study the speed and energy limitations of their resistive switching operation. Our picosecond time-resolution, real-time resistive switching experiments and numerical simulations demonstrate that tunable low-resistance states can be set by the application of 20 ps long, <1.7 V amplitude voltage pulses at 15 ps incubation times and switching energies starting from a few femtojoule. Moreover, we demonstrate that at nanometer-scale device sizes not only the electric field induced insulator-to-metal transition but also the thermal conduction limited metal-to-insulator transition can take place at time scales of 100s of picoseconds. These orders of magnitude breakthroughs can be utilized to design high-speed and low-power dynamical circuits for a plethora of neuromorphic computing applications from pattern recognition to numerical optimization.

IoT Based Remote Low Voltage Power Circuit Breaker System in Flood Areas

IoT Based Remote Low Voltage Power Circuit Breaker System in Flood Areas

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile

In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of ∼1018 cm−3 and a high drain length of ∼50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (Iamb) current. The proposed structure yields Iamb and Ioff as low as ∼10−18 A/μm and ∼10−17 A/μm respectively, while maintaining the Ion as ∼0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain Cgd and the gate–source Cgs capacitances for various device parameters.

Proposal and evaluation of Mg2Si-based vertical tunnel field effect transistor for enhanced performance

This work investigates the performance of silicon-on-insulator (SOI) based vertical heterojunction tunnel FET with magnesium silicide (Mg2Si) as source material (Mg2Si-VTFET) with silicon-based counterpart (Si-VTFET). The investigation utilizes SILVACO TCAD tool to analyse various metrics including electrical characteristics, radio-frequency performance, linearity, and distortion. Incorporation of low bandgap material at source forms hetero-junction at source-channel interface, thereby reducing the tunneling path and enhancing the tunneling rate of charge carriers. ON-state current (ION) and current switching ratio (ION/IOFF) for Mg2Si-VTFET improves by factor of approximately ∼ 105 and 102 times. Mg2Si-VTFET outperforms Si-VTFET in terms of ION current for low biasing voltages, transconductance (gm), gain-bandwidth-product (GBP), cut-off frequency (fT) and transit-time. However, Mg2Si-VTFET has better linearity and reduced distortions in terms of VIP2 and HD2 metrics. HD2 suppresses by 53.8 % for Mg2Si-VTFET over Si-VTFET. This suggests that Mg2Si-VTFET is better suited for applications requiring low distortion, such as in audio amplifiers or communication systems. Therefore, Mg2Si-VTFET shows strong candidacy over Si based counterpart for low power circuits.

Review on low power design of digital integrated circuits

Abstract With the rapid development of science and technology, integrated circuit (IC) plays an increasingly important role in our daily life. Moreover, due to the increasing reduction of chip process size, the IC had greatly improved on its integration and performance. However, because of the improvement of the system complexity and the widely applied to various mobile devices, power consumption becomes an important limitation of the development in chip design. Power consumption not only affects the chip package type and cost, but also causes the increasing of chip temperature, which will directly affect the reliability of chips. On the other hand, high power consumption will also harm the stability of chips. Low power design are becoming more and more imminent, so low-power design are becoming a tendency of designing digital integrated circuits. This paper firstly introduces the importance of nowadays IC research, some background principles and research process of integrated circuits, then analyses the current challenges of designing low-power ICs and also research the power consumption of digital integrated circuits, later explores and analyses the low-power design methods in two different ways. And finally summarize the research status on low-power design circuits with some relevant personal views and the vision to the future are also put forward.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Design and test of a sub-45 nm non-aligned double gate inverter in TCAD environment: static and dynamic analysis

ABSTRACT This work presents a sub-45 nm application-specific nanoscale single-device non-aligned double gate inverter (NADGI) with minimised gate and drain contacts. NADGI uses two devices of 25 nm channel length, i.e. NADGPFET and NADGNFET, giving maximum ON-current of 1.16 mA and 1.36 mA, respectively. The dynamic performance of the proposed structure was evaluated by applying ultra-high frequency, super-high frequency, and varying supply voltage/load capacitor. This work uses graphical method to determine the optimal supply voltage of the NADGI, the estimated values at 1 GHz and 10 GHz input frequency were 0.6 V and 0.7 V, respectively. When compared with the past works, the proposed inverter shows 82.4% improvement in propagation delay and 40% reduction in the supply voltage. Therefore, with improved design structure and response, the proposed inverter can be suitably used for high-frequency and low-power circuit design.

Development of a non-standard system for simplifying boolean functions

The object of this study is models of low-power digital logic circuits. The problem being solved is the effectiveness of the technique for simplifying Boolean functions to obtain optimal structures of logic circuits. A new theorem of a non-standard system of simplification of Boolean functions has been formulated, according to which in order to obtain a minimal function it will suffice to perform all non-redundant operations of simple and/or super-gluing of variables, which ultimately provides a minimal function in the main basis without using an implicant table. Thus, the problem of simplifying Boolean functions to the simplest normal equivalent is solved in one step. The interpretation of the result is that the properties of 2-(n, b)-design combinatorial systems make it possible to reproduce the definition of logical operations of super-gluing variables, to represent logical operations in a different way, and vice versa. This, in turn, ensures the establishment of the locations of equivalent transformations on the binary structure of the truth table and the implication of a systematic procedure for simplifying Boolean functions by an analytical method. Special feature of the results is that unambiguous identification of the locations of equivalent transformations is possible even when different intervals of the Boolean space containing the 2-(n, b)-design systems have common modules. It has been experimentally confirmed that the non-standard system improves the efficiency of simplifying Boolean functions, including partially defined ones, by 200–300 % compared to analogs. In terms of application, a non-standard system for simplifying Boolean functions will ensure the transfer of innovations to material production: from conducting fundamental research, expanding the capabilities of digital component design technology to organizing serial or mass production of novelties

A High-Performance, Secure Custom Electronics Circuit for Biopotential Measurement and Processing

Purpose: In this paper, we propose a secure wearable and portable device aiming to (i) monitor physical activity in medical and clinical rehabilitation, (ii) evaluate the subject's movements in sports environments, and (iii) monitor wellness indicators. Materials and Methods: The innovative low-power custom circuit can acquire, pre-process, digitalize, and transmit EMG signals to a Raspberry PI4 device via a low-energy Bluetooth module. The Raspberry PI4 is a hub that sends data to a cloud-based system for remote monitoring and processing. The best cybersecurity practices have been implemented: firewall, anti-DDoS and SELinux. Results: We have assessed the system's vulnerability before and after the system's hardening. SELinux makes the system safer and prevents unauthorized access to patients' data health by tampering with the devices. Conclusion: Adopting IoT systems in telemedicine requires greater attention to cybersecurity. It is necessary to implement security mechanisms to guarantee the privacy of patient's health data.

A Low-Power High-Sensitivity Photocurrent Sensory Circuit with Capacitive Feedback Transimpedance for Photoplethysmography Sensing.

This study presents an integrated analog front-end (AFE) tailored for photoplethysmography (PPG) sensing. The AFE module introduces a novel transimpedance amplifier (TIA) that incorporates capacitive feedback techniques alongside common drain feedback (CDF) TIA. The unique TIA topology achieves both high gain and high sensitivity while maintaining low power consumption. The resultant PPG sensor module demonstrates impressive specifications, including an input noise current of 4.81 pA/sqrt Hz, a transimpedance gain of 18.43 MΩ, and a power consumption of 68 µW. Furthermore, the sensory system integrates an LED driver featuring automatic light control (ALC), which dynamically adjusts the LED power based on the strength of the received signal. Employing 0.35 µm CMOS technology, the AFE implementation occupies a compact footprint of 1.98 mm × 2.475 mm.

Projected performance of Si- and 2D-material-based SRAM circuits ranging from 16 nm to 1 nm technology nodes.

Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS2 nFETs and WSe2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (-16%), reduced time to write (-72%) and lowered dynamic power (-60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications.

A 25 Mbps 15 ns Propagation Delay 150 kV/μs CMTI Configurable Dual-Channel Capacitive Digital Isolation Driver.

Electrical isolation devices are essential components for safeguarding the reliability of electronic systems under harsh conditions. Digital isolators are widely used in low-power circuits due to their high immunity to disturbances. In this paper, a capacitive digital isolator for high-efficiency power supply scenarios is proposed with a high common-mode transient immunity (CMTI) and high data transmission rate. The on-off keying (OOK) modulation technique is used to ensure a high speed and accurate signal transmission. A fully integrated high-voltage level-shift driver with an ns-scale delay is proposed for increasing the drive capacity. Post-simulation results in Cadence IC 6.1.7 with the standard 0.18 μm CMOS process show that the proposed architecture achieves a 25 Mbps data transmission rate and 15 ns typical propagation delay with output peak currents of 2 A/4 A, respectively. Meanwhile, a CMTI of more than 150 kV/μs is realized.

Surface crystallization effects on tellurium oxide thin films for low-power complementary logic circuit applications

Van-der-Waals-structured tellurium (IV) has demonstrated its potential as a promising building block for complementary logic device due to its superior electrical and optoelectronic features. Here, we demonstrated the novel approach for developing high-performance tellurium oxide (TeOX) thin film through TeOX formation and surface crystallization (SC). The crystalline structures and chemical bindings of the TeOX surfaces were carefully engineered by time- and temperature-dependent UV-ozone treatment and ALD-grown-Al2O3-assisted crystallization. The huge enhancement of device performance was achieved in the optimized SC-TeOX transistor, especially high on–off current ratio of 2.19 × 106, which can be ascribed to the synergistic effects of TeOX formation and SC process resulting in the enlarged bandgap, strong valence band edge localization, and the improved crystallinity. The performance enhancement mechanism was systematically studied by constructing SC-TeOX transistor with different TeOX region, where the TeOX creation in both Te channel and source/drain electrode regions dramatically improved performance owing to the decreased contact resistance and enhanced charge transport. Consequently, we achieved the high-performance low-power complementary logic circuits with SC-TeOX transistors, even reaching the maximum gain of 67.9 and low static power of 0.5 nW. Thus, this work demonstrates the great potentials of SC-TeOX transistor for developing advanced low-power complementary logic circuits.

INDIDO: A novel low-power approach for domino logic circuits

Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors.The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn’t entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach.The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18% and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parametres in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability.This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme

A mixed-logic design scheme utilizing pass-transistor logic (PTL) and dual-value logic (DVL) in combination with static CMOS logic for decoders in SRAMs is proposed. By using of the mixed-logic circuit, new n-Transistor (T) NAND/AND structures were provided for decoders, while achieving fewer transistors, faster speed, lower power dissipation as compared to traditional circuits, and having full-swing capability and good noise immunity. Experiments were conducted using TSMC 28 nm process for mixed-logic decoders, and the results show the superiority in terms of propagation delay and power dissipation, compared to the conventional corresponding circuits. A mixed-logic 2-4 decoder exhibits 36 % reduction in propagation delay and 10 % improvement in power dissipation; A mixed-logic 3-8 decoder exhibits 27 % reduction in propagation delay and 5.5 % improvement in power dissipation; While, A mixed-logic 4-16 decoder exhibits 30 % reduction in propagation delay and 5 % improvement in power dissipation; As well, A mixed-logic 5-32 decoder exhibits 34 % reduction in propagation delay and 6.3 % improvement in power dissipation.