Low On-state Resistance Research Articles

The influence of oxygen partial pressure on the properties of sputtered vertical NiO/β-Ga2O3 heterojunction diodes

In this work we present studies on the influence of oxygen partial pressure on the properties of sputtered vertical NiO/β-Ga2O3 heterojunction diodes. Obtained results shows substantial effect of oxygen partial pressure on the electrical properties of NiO/β-Ga2O3 heterojunction diodes. The diodes with NiO layers deposited in pure Ar shows Schottky-like I-V characteristics with low ideality factor of 1.05 and barrier height of 1.27 eV as well as low turn-on voltage close to 1V. On the other hand, diodes with NiO layer deposited in oxygen containing atmosphere shows typical p-n diode characteristics. The best electrical characteristics i.e. low on-state resistance of 2.85 mΩcm2, lack of defects and low ideality factor down to 1.07 at RT along with high breakdown voltage close to 900V without any junction termination, were obtained for diodes with NiO layers deposited at 50 % oxygen content. We have demonstrated that by optimization of oxygen partial pressure, the properties of NiO/β-Ga2O3 heterojunction diodes can be tuned and excellent electrical performance in terms of low-on state resistance, high breakdown voltage, low-leakage current and low ideality factor, can be obtained.

Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*

In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (V th) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a V th of 3.4 V, a low on-state resistance (R on) of 0.64 mΩ cm2, and a BV of 1245 V, while the PVG-HEMT device exhibits a V th of 3.7 V, an R on of 0.65 mΩ cm2, and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm−2, respectively, much higher than that for the VG-HEMT control group (1.0 GW cm−2). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.

Enhanced gate biasing resilience in asymmetric and double trench SiC MOSFETs towards generalized highly reliable power electronics

The gate oxide quality in SiC MOSFETs presents a significant challenge, particularly at temperatures exceeding 175 °C. This predicament arises from the gate oxide interface's propensity to trap or release charge carriers, compromising device ruggedness. In mainstream SiC MOSFETs, the gate oxide in the trench corner confronts the demanding task of enduring higher electric field strengths, thereby posing a substantial risk to overall device reliability. As a result, research entities are proactively involved in improving the SiC/oxide interfaces to enhance the devices' resilience against elevated E-field. This endeavor aims to maintain the favorable characteristics of the trench SiC MOSFETs, including low on-state resistance, minimal parasitic capacitance, and exceptional switching performance. Thus, the implementation of a streamlined process becomes crucial to fortify the trench corner, ultimately yielding boosted E-field immunity. In this report, our research focuses on enhancing the reliability of trench corner in SiC MOSFET devices. Specifically, we employ spacer etch technology to selectively shield the trench corner with high-K heterolayers, thereby enhancing the device's ability to withstand higher E-field strengths (59.2 % reinforcement) while mitigating the risk of hidden defects. Importantly, compared to the structure without protection, at high-K shielded layer contact angles ranging from 90 to 150°, the E-field decreases, correlated the enhanced reinforcement at larger angles. Furthermore, such technology enables higher E-fields and greater circuit capacity at the bottom of trench gate, leading to enhanced device reliability. Our studies confirm that the developed device structure exhibits simplicity, reliability, maturity, and controllability, rendering it suitable for large-scale integration applications.

Shared External Driver for VHF Converter With a Synchronous Rectifier Based on Matching Network Parameters Optimization

In order to reduce the conduction loss of diode, synchronous rectification is usually adopted in very-high-frequency (VHF) converters, in which the rectifier diode is replaced by a MOSFET with very low on-state resistance. And to ensure normal operation of the synchronous rectifier switch, it is necessary to design a suitable driver with accurate timing. The widely used self-oscillating resonant drive circuit has a limited range of duty cycle adjustment, and the body diode of synchronous rectifier switch has long on-state time and a large conduction loss. Therefore, based on the analysis and parameters optimization of matching network, a shared external drive circuit is put forward. That is, the drive signals of the inverter switch and the synchronous rectifier switch come from the same external oscillation signal. On the premise of ensuring accurate drive timing, it can improve the drive signal's duty cycle of synchronous rectifier switch, reduce the conduction loss of body diode, and improve the efficiency of converter. Then on the basis of the proposed drive circuit, a VHF converter prototype with operating frequency of 10 MHz, 13 V input and 8 V/10 W output is designed, and the feasibility of the proposed drive circuit is verified by simulations together with experiments.

Investigation of WBG based Power Converters used in E-Transportation

Nowadays, Uses for transportation are evolving in the direction of getting more electrified due to rising fuel costs and environmentally hazardous pollutants due to which The grid’s need for power is increasing dramatically. As the only solution for this is to diminish the power consumption of Electric Vehicles (EV). Enhanced component efficiency can lead to improved electric vehicle performance. Wide band gap (WBG) semiconductors, in particular silicon carbide (SiC) and Gallium Nitride (GaN), are ideal candidates of choice to address the recent growing demand in both high efficiency and great power density converters about electric vehicles. Due to their the capacity to switch at a high frequency, high temperature, high voltage, reduced size and reduced conduction losses makes them superior than Si semi-conductors. WBG devices have some properties which include rapid electron mobility, high breakdown field, and big band gap low on-state resistance and capacitance, lower co-efficient of thermal expansion (CTE) and high stability. This paper includes a study on WBG devices, their properties, and the increased efficiency of power converters i.e DC-DC boost converter and single-phase full bridge inverter using LTSpice simulation tool.

Degradation and Failure Mechanism of p-GaN Gate E-Mode GaN HEMTs

GaN-based power transistors are becoming pivotal devices for high power and high voltage operation due to their higher breakdown voltage, higher carrier mobility because of two-dimensional electron gas (2-DEG), better thermal resistance, higher frequency switching, and lower on-state resistance (RON) [1]. P-GaN gate E-mode GaN HEMTs have emerged as a center of extensive research to understand their operation and reliability [2]. However, one of the reasons the E-mode GaN HEMTs are not yet successfully utilized to their maximum potential is the lack of complete understanding of gate breakdown. Gate degradation of p-GaN gate E-mode GaN HEMT is less understood because of the complexities involving the operating conditions and variables such as gate length, the acceptor doping concentration in the p-GaN layer [3], p-GaN gate thickness, and design of the device [4-5]. To outline a consistent degradation mechanism, this work aims to present an electro-physical model of gate breakdown in p-GaN gate E-mode HEMTs.Lateral E-mode GaN HEMT devices with p-GaN gate configuration are used for this study. According to the Scanning Transmission Electron Microscopy (STEM) imaging of a new device, the AlGaN barrier is 10 nm thick, and the p-GaN cap is 65 nm. The gate-source and gate-drain lengths are 0.5 micrometer and 2.5 micrometer, respectively. The gate length defined by the p-GaN layer is 0.5 micrometer and the edges of the gate metal are pulled in from the top edge of the p-GaN layer by 40 nm. A 0.7 micrometer-long, source-connected field plate is over the p-GaN gate. The p-GaN gate is subjected to static stress to induce accelerated breakdown. Devices were stressed with HP 4155 Semiconductor Analyzer. The electrical measurements were performed with the source, drain, and substrate connected to the ground. FEI 200 Nova was used for Scanning Electron Microscopy (SEM) imaging and Focused Ion-Beam (FIB) milling. ARM JEM-200F with a Cs corrector was used for STEM.Our results show that time-to-fail is highly dependent on device operating conditions. We found no correlation between time-to-fail and initial gate current (IG0). Instead, a higher impact of temperature was found on the gate current of the device (IG) and time-to-fail at 100 °C. Gate failure at constant voltage stress was a single-stage failure. Under constant current stress, on the other hand, the gate shows a multi-stage failure. The breakdown mechanism depends on the impact of static stress on the gate degradation, starting with increased gate current leading to Schottky barrier leakage and finally to catastrophic contact failure. Our study shows that the metal/p-GaN interface at the gate finger becomes the weakest part of the gate stack, likely to be the initiation point of degradation. Metal/p-GaN interface and surface defects develop as percolation paths acting as leakage sources, and nano-cracks have been observed in the gate cap. FA also shows physical degradation at the metal/p-GaN cap due to electrical stress. Observed physical damage in the gate region is correlated to the gate leakage characteristics to develop an electro-physical failure model for gate breakdown in p-GaN gate E-mode GaN HEMTs.

A systematic study on the efficacy of low-temperature GaN regrown on p-GaN to suppress Mg out-diffusion

Embedding p-type gallium nitride (p-GaN) in AlxGa1-xN-based thin films has garnered significant interest as a versatile structure for bandgap engineering such as tunnel/super-junctions or current blocking/guiding functions in electronic devices. However, Mg, a p-GaN dopant, has an undesirable diffusive capacity into the nearby thin films at a high growth temperature (>1,000°C), resulting in structural challenges in device design. This study systematically investigated the low-temperature GaN (LT-GaN) layer regrown on p-GaN that suppresses Mg diffusion according to metal–organic chemical vapor deposition growth conditions. Prototype Al0.3Ga0.7N (40 nm)/GaN (140 nm) high-electron-mobility transistors (HEMTs) were regrown with LT-GaN on p-GaN (300 nm), and a high two-dimensional electron gas (2DEG) density of 3.13E12 cm−2 was achieved by inserting a 100-nm-thick LT-GaN layer grown at 750°C; in contrast, only 1.76E10 cm−2 2DEG density was obtained from Al0.3Ga0.7N/GaN HEMTs regrown directly on p-GaN (Mg: 4.0E19 cm−3). The fabricated Al0.3Ga0.7N/GaN HEMTs with 100-nm-thick LT-GaN demonstrated a high drain current density of 84.5 mA/mm with a low on-state resistance of 31 Ω·mm. The AlxGa1-xN/LT-GaN/p-GaN platform demonstrated here paves the way for various III-nitride-based structures with embedded p-GaN.

(Invited) Fabrication and Device Performance of 2.7 Kv/2.5A NiO/Ga2O3 Heterojunction Power Rectifiers

In this study, The fabrication of a p-n junction NiO/Ga2O3 rectifier in which we employ a bilayer NiO structure with two different doping levels to achieve both high breakdown voltage and low on-state resistance was described. The band alignment of the NiO to the Ga2O3 was measured. Selective wet and dry etch processes for removing NiO from the underlying Ga2O3 was developed. Finally, the dc and switching performance of the rectifiers was characterized. The maximum breakdown voltage was 2.7 kV for a 1 mm diameter rectifier, with 2.5 A forward current and on/off ratio > 108 over a broad range of switching voltages. The reverse recovery time was limited by the measurement circuit but was < 100 µs. These results show the promise of heterojunction rectifiers based on Ga2O3 for future generations of power switching applications. Figure 1

A Non-Isolated High Voltage Gain DC–DC Converter Suitable for Sustainable Energy Systems

A non-isolated high gain DC–DC converter with magnetic coupling and a VM circuit is proposed in this study. By the use of the appropriate coupled inductor turn ratio, the output voltage of the recommended topology can be raised. The VM circuit is used to boost the voltage gain even further as well as to clamp the voltage spike across the switch, which results in a lower voltage on the switch. As a result, a MOSFET switch with a lower ON-state resistance (RDS-ON) is used which, in turn, causes the conduction losses to be reduced and the entire system efficiency to be raised. Another advantage of the proposed structure is the ZCS of the diodes, which reduces the voltage drop losses caused by the regenerative diodes. The function modes analysis and the theoretical equations are accomplished. A comparison survey with other prior works is being developed to investigate the competency of the proposed converter. Based on this, the higher voltage gain and efficiency as well as the lower voltage stress on the semiconductors can be achieved by the proposed converter compared to the other converters. The effectiveness of the proposed converter is confirmed by the experimental results at a laboratory-scale operating under 150 V output voltage with a 96% efficiency at the 150 W full load and a 25 kHz switching frequency.

A Three-Level Resonant DAB Converter Featuring Minimized Circulating Losses for EV Battery Charging

A three-level modified series-parallel bidirectional isolated dc <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> dc resonant converter (TL-MSPBRC) is proposed for EV battery charging. The converter's performance is enhanced for wide load conditions as the modified series-parallel resonant tank is formed by considering the parasitics in the transformer. The first-harmonic approximation (FHA) equivalent circuit model is employed to analyze the converter characteristics for the frequency modulation technique. This converter has high conversion efficiency in charging and discharging operations because of the soft-switching capability of the power switches in the primary and secondary bridges. In addition, low on-state resistance switches in the three-level primary bridge minimize the conduction losses. A 3.3-kW converter prototype with a battery voltage range of 230 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 300-V is developed to validate the design method and the simulation results. The proposed converter has minimized circulating losses, good short-circuit protection, and excellent efficiency of 97.7% at the rated power level.

Novel four-port RF phase change switches based on GeTe thin film

An indirect-heated phase-change switch (PCS) using germanium telluride (GeTe) has been fabricated using thermal actuation driven by thin film heater on the model. Switches require a low ON-state resistance and a high OFF-state resistance with OFF/ON resistance ratio of 105. The finite element analysis simulation is applied to simulate the temperature of individual node GeTe with different microwave heating pulses. Finally, in order to reduce the phase-change time and increase the switching speed of indirectly heated switching structures, a new four-port indirectly heated phase change switching structure is proposed. In this paper, the heat dissipation of the switch is increased by etching deep grooves on the back of the switch. This structure obviously reduces the phase change time compared to conventional indirectly heated phase change switches the time between ON-state and OFF-state is reduced by more than 19% and the total process is reduced by more than 47%. The GeTe PCSs with etched grooves not only significantly increases the switching speed, but also reduces the risk of recrystallization of the phase change material.

Contemporary materials for semiconductor switches in an isolated bidirectional DC-DC converter using a closed loop system with linear quadratic regulator control

This research seeks to create a novel bidirectional DC-DC converter capable of high step-up/down power transfer for diverse applications, such as grid systems, energy backup systems, fuel cell vehicles and hybrid electric vehicles. The converter features an inductor linked to an electric power grid to facilitate multi-layer energy conversion with galvanic isolation for improved voltage ratio and galvanic isolation. Notable among its features is this converter's capacity to recycle energy from a leaky inductor without needing additional snubber mechanisms or clamped circuits. To facilitate efficient operation, the converter employs power switches capable of soft switching both step-up and step-down modes. This option permits using MOSFETs with low on-state resistance, which is advantageous due to reduced voltage endurance at the primary side. This research explores the application of a linear quadratic regulator (LQR) for use with a constant frequency bidirectional DC-DC converter. Leveraging the high-order nature of converters, LQR controllers make full use of their potential by offering rapid dynamic response time, reliability and minimal changes in settling time for an array of operating conditions. Thorough analyses were carried out into the availability and stability conditions of an LQR controller in step-up mode using MATLAB/Simulink simulation results as evidence. This study also emphasizes the significance of performance and effectiveness in electronic power-switching devices, which rely heavily on material properties for operation. While silicon has traditionally been employed for these switches, advances in material science have seen wider band-gap semiconductors adopted to improve switching device performance. Therefore, this research encompasses selecting and implementing appropriate semiconductor materials into power electronic switches used by DC-DC converters.

Design and Implementation of Nonisolated High Step-Up DC-DC Converter

This article presents a novel structure for a high step-up DC-DC converter. The proposed converter offers several advantages, including a simple structure, high voltage gain, high efficiency, reduced voltage stress on the semiconductors, and fewer components. A two-winding coupled inductor has been employed to enhance the output voltage level in this topology. The suggested structure has only one power switch with low ON-state resistance (RDS-ON), reducing power losses. Moreover, the zero-voltage switching (ZVS) and zero-current switching (ZCS) features of the diodes of the proposed converter result have improved overall efficiency. To evaluate and ascertain the enhanced performance of this configuration, the study of different modes of operation, steady-state investigation, and a comparative study between the proposed and other relevant topologies are presented. A laboratory prototype is designed and implemented with an input voltage of 12 V, an output voltage of 150 V, and a 200 W rated power level under a 50 kHz switching frequency. The maximum efficiency of the recommended topology is measured at the rated output power, equal to 96.98%. Also, for an output power range from 50 W to 350 W, the efficiency is obtained higher than 95%.

A ZVS-Based Non-Isolated High Step-Up DC–DC Converter With Low Voltage Stress for Renewable Applications

A high gain soft switched step-up DC-DC converter is presented in this paper. High gain is achieved at lower duty and turns ratio with a pair of coupled inductors and a voltage multiplier. In addition, an active clamp is incorporated to reduce the voltage stress across the main switch. Hence, switches with lower on-state resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R_dson</i> ) and lower voltage ratings are employed, reducing both conduction losses and cost. It additionally helps in achieving zero voltage switching (ZVS) to both MOSFETs. By recycling the leakage energy of the coupled inductors, voltage gain is further increased. It also helps to accomplish zero current switching (ZCS) turn-on and off of diodes. This further reduces losses and increases further efficiency. Moreover, the reverse recovery problem of the diodes is also mitigated. The working principle, steady-state analysis, and design guidelines have been carried out. Finally, a 500 W hardware set up with an input voltage range of 20-24 V and output of 400 V at a switching frequency of 50 kHz is built to validate the performance of the proposed converter. The operating efficiency at full load is observed as 95.11%.

Evaluation of turn-off dV/dt controllability and switching characteristics of 1.2 kV GaN polarisation superjunction heterostructure field-effect transistors

Gallium nitride (GaN) devices inherently offer many advantages over silicon power devices, including a higher operating frequency, lower on-state resistance and higher operating temperature capabilities, which can enable higher power density and more efficient power electronics. Turn-off dV/dt controllability plays a key role in determining common-mode voltage in electrical drives and traction inverter applications. The fast-switching edges of GaN can introduce challenges such as electromagnetic interference, premature insulation failure and high overshoot voltages. In this paper, the device working principle, characteristics and dV/dt controllability of 1.2 kV GaN polarisation superjunction (PSJ) heterostructure FETs (HFETs) are presented. The effect of gate driving parameters and load conditions on turn-off dV/dt are investigated. It is shown that in PSJ HFETs the dV/dt can be effectively controlled to as low as 1 kV μs−1 by controlling the gate, with a minimum increase in switching losses. These results are highly encouraging for the application of the devices in motor drives.

Analysis and Design of a New High Voltage Gain Interleaved DC–DC Converter with Three-Winding Coupled Inductors for Renewable Energy Systems

In this article, a new non-isolated interleaved DC–DC converter is proposed to provide a high voltage conversion ratio in renewable energy systems. The converter configuration is composed of a two-phase interleaved boost converter integrating a voltage-lift capacitor and three-winding coupled inductor-based voltage multiplier modules to achieve high step-up voltage conversion and reduce voltage stresses on the semiconductors (switches and diodes). The converter can achieve a high voltage conversion ratio when working at a proper duty ratio. The voltage stresses on the switches are significantly lower than the output voltage, which enables engineers to adopt low-voltage-rating MOSFETs with low on-state resistance. The switches can turn on under zero-current switching (ZCS) conditions because of the leakage inductor series reducing switching losses. Some diodes can naturally turn off under ZCS conditions to alleviate the reverse–recovery issue and to reduce reverse–recovery losses. The input current has small ripples due to the interleaved operation. The leakage inductor energy is recycled and voltage spikes on the switches are avoided. The proposed converter is suitable for applications in which high voltage gain, high efficiency and high power are required. The principle of operation, steady-state analysis and design considerations of the proposed converter are described in detail. In addition, a closed-loop controller is designed to reduce the effect of input voltage fluctuation and load change on the output voltage. Finally, a 1000 W laboratory prototype is built and tested. The theoretical analysis and the performance of the proposed converter were validated by the experimental results.

Effect of High-Pressure GaN Nucleation Layer on the Performance of AlGaN/GaN HEMTs on Si Substrate.

A high-pressure (HP) GaN nucleation layer (NL) was inserted between AlGaN buffer and an unintentionally doped (UID) GaN layer of an AlGaN/GaN HEMT on Si. The XRD and TEM showed that when the V/III ratio was optimized during the HP-GaN NL growth, the edge dislocation density in the HP-GaN NL layer could be reduced significantly. Experimental results exhibited a lower off-state leakage current, higher maximum ID and Gm (corresponding to 22.5% and 21.7% improvement, respectively), and lower on-state resistance. These results demonstrate that the electrical properties of the AlGaN/GaN HEMT can be improved through the insertion of a HP-GaN NL.

High Current Density Trench CAVET on Bulk GaN Substrates with Low-Temperature GaN Suppressing Mg Diffusion

We report that, for the first time, a low-temperature GaN (LT-GaN) layer prepared by metal–organic chemical vapor deposition (MOCVD) regrowth was used as a Mg stopping layer (MSL) for a GaN trench current–aperture vertical electron transistor (CAVET) with p-GaN as a carrier blocking layer (CBL). Inserting LT-GaN on top of the p-GaN effectively suppresses Mg out-diffusion into the regrown AlGaN/GaN channel, contributing to the high current capability of GaN vertical devices with a p-GaN CBL. With different MOCVD growth conditions, MSLs inserted in trench CAVETs were comprehensively investigated for the influence of MSL regrowth temperature and thickness on device performance. With the best on-state current performance obtained in this study, the trench CAVET with a 100 nm thick MSL regrown at 750 °C shows a high drain current of 3.2 kA/cm2 and a low on-state resistance of 1.2 mΩ∙cm2. The secondary ion mass spectrometry (SIMS) depth profiles show that the trench CAVET with the 100 nm thick MSL regrown at 750 °C has a dramatically decreased Mg diffusion decay rate (~39 nm/decade) in AlGaN/GaN channel, compared to that of the CAVET without a MSL (~104 nm/decade). In developing GaN vertical devices embedded with a Mg-doped p-type layer, the LT-GaN as the MSL demonstrates a promising approach to effectively isolate Mg from the subsequently grown layers.

Comparisons and Evaluations of Silicon and Wide Band Gap Devices at Cryogenic Temperature

In this article, the static and dynamic characterizations for semiconductors with different materials, including silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), are evaluated and compared at room temperature and cryogenic temperature (liquid nitrogen temperature). For static characterizations, the on-state resistance and threshold voltage are evaluated. For dynamic characterizations, the turn-on switching loss, turn-off switching loss, and dynamic on-state resistance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> ) are evaluated. The results demonstrate that Si and GaN based semiconductors have improved performances with lower on-state resistance and faster switching speed at low temperature operations. For SiC based semiconductors, the on-state resistance increases significantly at cryogenic temperature. The switching speed is reduced dramatically for the evaluated 1.2 kV SiC metal oxide semiconductor field effect transistors (MOSFETs) at cryogenic temperature. This makes it less attractive for cryogenic applications. For the evaluated 650 V and 900 V SiC MOSFETs, the switching speed remains almost unchanged at low temperature. GaN high electron mobility transistor (HEMT) demonstrates a fast turn-on switching speed at low temperature, where the device's <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv/dt</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di/dt</i> are almost doubled when compared with room temperature. In addition, the dynamic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds(on)</sub> of the evaluated GaN HEMTs also decreases at low temperatures. The evaluation results can serve as guidelines for cryogenic power electronics applications. Meanwhile, the future work for semiconductors cryogenic characterizations is discussed.

Design, Simulation and Optimization of an Enhanced Vertical GaN Nanowire Transistor on Silicon Substrate for Power Electronic Applications

A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.