Low Off-state Leakage Current Research Articles

Low-Dispersion, High-Voltage, Low-Leakage GaN HEMTs on Native GaN Substrates

In this paper, the advantages of GaN high electron mobility transistors (HEMTs) grown on native GaN over GaN/Si or GaN/sapphire substrates are investigated and correlated with epitaxial material quality. Transmission electron microscopy plan-view and cross-sectional analyses of GaN/GaN reveal dislocation densities below ${1} \times {10}^{{6}}$ cm−2, which is at least three orders of magnitude lower than that of GaN/Si or GaN/sapphire. In the case of GaN/Si, the dislocations not only originate from the substrate/nucleation layer interface, but also the strain relief and isolation buffer stacks are main contributors to the dislocation density. GaN/GaN HEMTs show superior electrical and thermal performance and feature three orders of magnitude lower OFF-state leakage. The current collapse (also referred to as current dispersion or $R_{ \mathrm{\scriptscriptstyle ON}}$ -increase) after stress bias is less than 15% compared with 50% in the case of GaN/Si. A 2% drop of the ON-state current due to self-heating in dc operation when compared with 13% and 16% for GaN/Si and GaN/sapphire, respectively. The GaN/Si thermal performance becomes comparable to that of GaN/GaN only after substrate removal. Therefore, GaN/GaN provides high ON-state current, low OFF-state leakage current, minimal current collapse, and enhanced thermal power dissipation capability at the same time, which can directly be correlated with the absence of high dislocation density.

Reverse-Blocking Normally-OFF GaN Double-Channel MOS-HEMT With Low Reverse Leakage Current and Low ON-State Resistance

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$ . Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved.

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Ultra-low rate dry etching conditions for fabricating normally-off field effect transistors on AlGaN/GaN heterostructures

Enhancement-mode transistors with uniform turn-on threshold voltage (Vth) can be achieved using low damage and low rate gate recess etching techniques. In this work, dry etching conditions for a AlGaN/GaN heterostructure with an ultra-low etching rate of 1.5 nm/min were demonstrated and we succeeded the possibility to achieve a low etch rate of an AlGaN/GaN heterostructure in a Cl2/BCl3 plasma using inductively coupled plasma (ICP). The etching development was successfully implemented in the achievement of a normally-off GaN/AlGaN based transistor. The optimal recess depth was determined after fabrication of various devices with different recess depth values and with various dry etching conditions and after examining the performances of fabricated devices various conditions, and determining the dependence of recess time. The optimized etching condition resulted in low damage and smooth morphology of the etched AlGaN/GaN surfaces. Fine control of the depth of the gate region recess was achieved for the AlGaN/GaN heterostructure without any etch-stop layer, and validated for the fabrication of field effect transistors (FETs) using conventional processes. The fabricated normally-off Al2O3/AlGaN/GaN MOSFETs delivered a high positive Vth of +5.64 V with a low off-state leakage current of ∼10−7 A/mm and lower current collapse.

Improvement of Subthreshold Characteristic of Gate-Recessed AlGaN/GaN Transistors by Using Dual-Gate Structure

The subthreshold characteristic of gate-recessed high-electron-mobility transistors (HEMTs) using dual-gate (DG) architectures is systematically studied. The recessed DG structure can effectively shift the threshold voltage ( ${V}_{\text {th}}$ ) in the positive direction. Different from the complex function expression between ${V}_{\text {th}}$ and AlGaN thickness ( $\text{t}_{b}$ ) in the recessed single-gate (SG) device, the variation of $\text{V}_{\text {th}}$ with ${t}_{b}$ is monotonic in the recessed DG devices. Recessed DG device exhibits a low off-state leakage current of $\sim {3}\times {10}^{{-10}}$ A/mm and gate induced drain leakage is effectively improved. A higher $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ range of recessed DG devices broadens about 2 times and provide a wider range of ${t}_{b}$ than that of recessed SG devices. The DG structure has a stronger modulation effect on drain–source resistance ( ${R}_{\text {ds}}$ ) and gate–drain resistance ( ${R}_{\text {gd}}$ ) than the SG devices. A lower subthreshold swing (SS) of ~100 mV/dec is obtained by recessed DG design. Due to the second gate inducing the lateral extension of depletion region between the first gate and drain, the off-state leakage and first gate reverse leakage have been significantly improved. Therefore, the recessed DG architecture design can effectively improve the fluctuation of SS and off-state current versus the different AlGaN barrier thickness.

A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action

In this paper, we demonstrate a tunnel dielectric-based junctionless transistor, referred as TD JLT, which consists of a thin dielectric layer in the middle of the channel region of a JLT leading to a drastically reduced parasitic bipolar junction transistor (BJT) action. Using calibrated 2-D simulations, we show that the proposed TD JLT has a significantly low off-state leakage current due to the presence of a tunneling barrier, and an enhanced source-to-channel barrier height, which results in a diminished parasitic BJT action in the off-state. Further, the proposed TD JLT exhibits an extremely high $I_{{{ \mathrm{\scriptscriptstyle ON}}}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $\sim 1.1 \times 10^{{{\sf{ 7}}}}$ for a channel length of 20 nm and a significant( $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ ratio of $\sim 10^{{{\sf{ 2}}}}$ even for a channel length of 10 nm.

Monolithic integration of InGaAs n-FETs and lasers on Ge substrate.

We report the first monolithic integration of InGaAs channel field-effect transistors with InGaAs/GaAs multiple quantum wells (MQWs) lasers on a common platform, achieving a milestone in the path of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers used for realizing transistors and lasers were grown epitaxially on the Ge substrate using molecular beam epitaxy (MBE). A Si-CMOS compatible process was developed to realize InGaAs n-FETs with subthreshold swing SS of 93 mV/decade, ION/IOFF ratio of more than 4 orders of magnitude with very low off-state leakage current, and a peak effective mobility of more than 2000 cm2/V·s. In addition, fabrication process uses a low overall processing temperature (≤ 400 °C) to maintain the high quality of the InGaAs/GaAs MQWs for the laser. Room temperature electrically-pumped lasers with a lasing wavelength of 1.03 µm and a linewidth of less than 1.7 nm were realized.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high $I_{\mathrm{\scriptscriptstyle ON}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ratio of $\sim 10^{8}$ . Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping ( $N_{D} \geq 2 \times 10^{19}$ cm $^{-3}$ ) is due to a shielding effect initiated by the band-to-band tunneling.

Dynamic Memory Cells Using MoS2 Field-Effect Transistors Demonstrating Femtoampere Leakage Currents.

Two-dimensional semiconductors such as transition-metal dichalcogenides (TMDs) are of tremendous interest for scaled logic and memory applications. One of the most promising TMDs for scaled transistors is molybdenum disulfide (MoS2), and several recent reports have shown excellent performance and scalability for MoS2 MOSFETs. An often overlooked feature of MoS2 is that its wide band gap (1.8 eV in monolayer) and high effective masses should lead to extremely low off-state leakage currents. These features could be extremely important for dynamic memory applications where the refresh rate is the primary factor affecting the power consumption. Theoretical predictions suggest that leakage currents in the 10(-18) to 10(-15) A/μm range could be possible, even in scaled transistor geometries. Here, we demonstrate the operation of one- and two-transistor dynamic memory circuits using MoS2 MOSFETs. We characterize the retention times in these circuits and show that the two-transistor memory cell reveals MoS2 MOSFETs leakage currents as low as 1.7 × 10(-15) A/μm, a value that is below the noise floor of conventional DC measurements. These results have important implications for the future use of MoS2 MOSFETs in low-power circuit applications.

Controlling BTBT-Induced Parasitic BJT Action in Junctionless FETs Using a Hybrid Channel

In this brief, we demonstrate for the first time that the presence of a hybrid channel, which consists of a p+ layer below the n+ active device layer in a junctionless (JL) FET, leads to a drastically reduced BTBT-induced parasitic BJT action. Using calibrated 2-D simulations, we show that the JLFET with a p+ layer [which we call hole sink (HS)] has a significantly low OFF-state leakage current due to an increased tunneling barrier width, an enhanced source-to-channel barrier height, and a better provision for collecting the band-to-band tunneling (BTBT) generated holes, which results in a diminished parasitic BJT action in the OFF-state. Further, the proposed HS JLFET shows an extremely high ON-state to OFF-state current ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ) ratio of $\sim 10^{7}$ for a channel length of 10 nm and a significant ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ) ratio of $\sim 10^{4}$ even for a channel length of 5 nm.

1.48-kV enhancement-mode AlGaN/GaN high-electron-mobility transistors fabricated on 6-in. silicon by fluoride-based plasma treatment

Enhancement-mode AlGaN/GaN high-electron-mobility transistors (HEMTs) were fabricated on a Si substrate by fluorine plasma treatment without pre-etching. The threshold voltage shifted from −8 to 2.3 V, effectively converting the depletion-mode HEMT to the enhancement-mode HEMT. The leakage current was reduced by two orders of magnitude by CF4 plasma treatment. The device exhibited a superior performance with a maximum drain saturation current of 210 mA/mm at VGS = 10 V and a peak gain of 44.1 mS/mm. A low off-state gate leakage current of 10−6 mA/mm, ION/IOFF ratio of approximately 108, and high breakdown voltage of 1480 V were obtained.

Improvement of Germanium Channel Nmosfet By Using Fluorine Co-Implant Methods

1.Background/ Objectives and Goal Ge has been investigated as a high mobility (both hole and electron) channel material as a substitute for silicon channels in order to boost the device performances. In this paper, we successfully fabricated the Ge nMOSFETs by using fluorine co-implant method. The Ge nMOSFETs by using fluorine co-implant method has good performance with ION/IOFF ratio of ~8.6×103 at VDS = 1V and the subthreshold swing of 382 mV/dec. 2.Methods Fig. 1 illustrates the process steps and structure of our Ge nMOSFETs by using F co-implant methods. We use (100)-oriented p-type Ge wafer with resistivity 0.1~0.6 Ω-cm as the starting material. Firstly, a 400 nm field oxide was deposited on p-type Ge substrates after diluted HF cyclic surface clean. The source/drain regions were defined by photolithography, and subsequently the oxide was etched by BOE. Then a implantation was used to create an n+ source/drain with P and F co-implant at different dose and energy. Following by 100nm SiO2 capping layer, dopant activation with different sequence were accomplished through rapid thermal annealing (RTA) at 600 °C in N2. The split table of dose/energy and RTA sequence was shown in table 1. After defining the active region, a GeO2 (~2 nm) was formed at 520°C for 30 s in pure O2 ambient (~1030 mBar) and then an Al2O3 (5 nm) was covered. 3.ExpectedResults/Conclusion/Contribution Fig. 2 shows the I-V characteristics of co-implant n+-p Ge junction for different annealing sequence, we can observe that the reverse leakage currents of n-Ge contacts decreased. The sequence splits are the P implantation following by annealing at 1 minute and then F implantation following by annealing at 1minute / 2 minutes. It’s obvious that the F could passivate the defect through P implantation by sufficient thermal annealing in the P+F@RTA_1+2min co-implant sample with low reverse leakage current than the P+F@RTA_1+1minsample. Fig. 3 shows the ID-VGS transfer characteristic of the control sample and the P+F@RTA_1+2min co-implant sample of nMOSFETs with W/L =100 μm /10 μm. The measurement voltage were in the linear region at VDS = 0.1 V and the saturation region at VDS = 1 V. We can observe that the co-implant nMOSFET have superior ION current, low IOFF current, ION/IOFF ratio and good subthreshold swing. The ION/IOFF ratio of the co-implant nMOSFET was of ~8.6×103 at VDS = 1V and the subthreshold swing was of 382 mV/dec. The white line cutting is the gate dielectric GeO2 (~2 nm) and Al2O3(5 nm) on top of the Ge substrate. The Ge-nMOSFET and n+-p Ge junction device have been demonstrated by F co-implant methods on p-type Ge substrate. The F implantation can passivate the vacancies in Ge substrate and enhance the overall activated fraction of the dopant in Ge. The shallow junction, low off-state leakage current, and low series resistance could be achieved. Moreover, we also use the best condition to fabricate the Ge n-MOSFET, and superior IONcurrent, low IOFF current, ION/IOFF ratio, good subthreshold swing, and low RSD could be realized. The co-implant methods have great potential for leakage current improvement and shallow junction in the conventional Ge process. REFERENCES [1]M. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, R. Kotlyar,M. Metz, N. Zelick, and R. Chau, “High Mobility Si/SiGe Strained Channel MOS Transistors with HfO2/TiN Gate Stack,”IEEE International Electron DevicesMeeting,p.28, Dec. 2003 [2]T. Krishnamohan, C. Jungemann, and K. C. Saraswat, “A Novel, Very High Performance, Sub-20 nm Depletion-Mode Double-Gate (DMDG) Si/Si,Ge(l.,jSi Channel PMOSFET,” in IEDM Tech. Dig., 2003, pp. 687-690. Figure 1

New approach to developing LC materials for IDS driving on reflective displays

As usage time for portable electronic terminals increases, associated problems regarding such extended use (e.g., battery holding times and eyestrain) are highlighted. Within the domain of power saving, we previously developed an idling stop (IDS) driving that avoids unnecessary refresh. Moreover, for reducing eyestrain to the highest extent possible, we calculated a luminance change in IDS driving that is not perceived as flickering by humans, via the use of a temporal modulation transfer function. According to the results of such calculations, a liquid crystal mixture that suppresses luminance changes perceived by humans was hence constructed. With the combined use of the liquid crystal mixture and a c-axis-aligned crystal oxide semiconductor with low off-state leakage current, a display could be developed wherein leakage current in IDS driving could be significantly reduced, along with enjoyed benefits of prolonged refresh intervals and power savings. The subject display is very eye-friendly, with less flickering than comparable technologies.

Organic Microelectromechanical Relays for Ultralow-Power Flexible Transparent Large-Area Electronics

This paper presents the development of electrostatically actuated polymer-based microelectromechanical relays as a potential replacement for organic field-effect thin-film transistors in order to enable near-zero-power flexible transparent large-area electronics. A low-temperature five-mask surface-micromachining process is developed to fabricate two types of prototype relays: purely polymeric and partially polymeric (inorganic–organic hybrid) relays. Experimental results demonstrate the operation of the prototypes as a switch, showing immeasurably low OFF-state leakage current ( $\sim 10$ fA), abrupt switching behavior and high ON/OFF-current ratio (>105 over an effective input voltage swing of ≤100 mV), small hysteresis voltages (≤100 mV), and low contact adhesive forces ( $\mu \text{m}^{2})$ . The influence of temperature on switching characteristics, including hysteresis voltages, is investigated as well.

AlGaN/GaN FinFET With Extremely Broad Transconductance by Side-Wall Wet Etch

AlGaN/GaN-based fin-shaped field-effect transistors with very steep side-wall have been fabricated by utilizing electron-beam lithography and subsequent anisotropic side-wall wet etch in tetramethyl ammonium hydroxide solution. The investigate device demonstrated extremely broad transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) ranging from ~0 to ~8 V at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 10 V, which is essential for high linearity device performance. Pulse measurement showed that the device exhibits negligible gate lag, but still suffers from drain lag. The device with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> of 17 μm exhibited excellent OFF-state characteristic with subthreshold swing of ~58 mV/decade, low OFF-state leakage current of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> A, and breakdown voltage of ~400 V at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -9 V.

Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates

By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio ( $\sim 10^{10}$ ), steep sub-threshold swing ( $66\sim 108$ mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.

High-voltage normally OFF GaN power transistors on SiC and Si substrates

Abstract

Channel length dependence of field-effect mobility of c-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Field-effect transistors (FETs) with c-axis-aligned crystalline In–Ga–Zn–O (CAAC-IGZO) active layers have extremely low off-state leakage current. Exploiting this feature, we investigated the application of CAAC-IGZO FETs to LSI memories. A high on-state current is required for the high-speed operation of these LSI memories. The field-effect mobility μFE of a CAAC-IGZO FET is relatively low compared with the electron mobility of single-crystal Si (sc-Si). In this study, we measured and calculated the channel length L dependence of μFE for CAAC-IGZO and sc-Si FETs. For CAAC-IGZO FETs, μFE remains almost constant, particularly when L is longer than 0.3 µm, whereas that of sc-Si FETs decreases markedly as L shortens. Thus, the μFE difference between both FET types is reduced by miniaturization. This difference in μFE behavior is attributed to the different susceptibilities of electrons to phonon scattering. On the basis of this result and the extremely low off-state leakage current of CAAC-IGZO FETs, we expect high-speed LSI memories with low power consumption.

Enhancement Mode (E-Mode) AlGaN/GaN MOSFET With $10^{-13}$ A/mm Leakage Current and $10^{12}$ ON/OFF Current Ratio

Postgate annealing (PGA) in N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> atmosphere at 300°C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of '10-13 A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> . At 250°C, the device still exhibits a low OFF-state leakage current of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> A/mm and high ON/OFF current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> . Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFFstate leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA.