Design Of Low Noise Amplifier Research Articles

V-Band GaAs Metamorphic Low-Noise Amplifier Design Technique for Sharp Gain Roll-Off at Lower Frequencies

In this letter, we present the design of a V- band low-noise amplifier for intersatellite crosslink receivers. The test vehicle, realized on industrial metamorphic gallium arsenide technology, operates from 57 to 66 GHz exhibiting 23-dB gain and an average 1.8-dB noise figure. Particular attention was devoted to the analysis and synthesis of an alternative bias injection topology to obtain a sharp gain roll-off at lower frequencies, thus avoiding the insertion, at system level, of an image-reject filter.

Design of reconfigurable multi-band low-noise amplifiers for 802.11ah/b/g and DCS-1800 applications

In this paper two reconfigurable multi band low-noise amplifiers, namely LNA1 for 802.11ah/b/g and LNA2 for 802.11ah/b/g, DCS-1800 applications using tank circuits are presented. Dual feedback is used to achieve multi band operation in both the LNAs. Power dissipation of the LNAs is reduced by employing current-reuse and forward body-biasing in the first stage of the LNAs. The novelty of the proposed approach lies in the fact that the reconfigurability of the LNAs for multi bands is achieved using simple tank circuits without requiring any additional biasing arrangement. The LNAs are designed using UMC 180 nm RFCMOS process. The post layout simulation results of LNA1 showed a power gain of 9.3 dB with noise figure of 3.7 dB, IIP3 of −2.19 dBm, DC power dissipation of 16.5 mW at 900 MHz and a power gain of 10.6 dB, noise figure of 3.1 dB, IIP3 of −2.7 dBm at 2.4 GHz. In LNA2 one common-source stage is added for further gain improvement and one more tank circuit is added to operate it additionally in GSM band, namely DCS-1800. Post layout simulation of LNA2 showed a power gain of 16.1 dB with noise figure of 4.6 dB, IIP3 of −6.57 dBm, DC power dissipation of 24.9 mW at 900 MHz; a power gain of 14.7 dB with noise figure of 5.4 dB, IIP3 of −4.34 dBm at 1.8 GHz and a power gain of 16.2 dB, noise figure of 3.6 dB, IIP3 of 0.57 dBm at 2.4 GHz.

Analysis and Design of Harmonic Rejection Low Noise Amplifier with an Embedded Notch Filter

This paper presents the analysis and design of the harmonic rejection (HR) low-noise amplifier (LNA) with the fully passive source degeneration notch filter. The proposed HR LNA provides the rejection for the strong harmonics ( 3 r d ) of the local oscillator (LO) frequencies, where the HR mixer does not provide sufficient HR performance. The proposed 3 r d harmonic notch filter modulates the source degeneration factor and the impedance matching performance thereafter. This effect further helps the blocking of the harmonic signal. The proposed LNA provides 11 dB gain at the fundamental frequency (2.1 GHz) while rejecting the 3rd harmonic component by 37 dBc. Compared to the conventional LNA, the 3rd harmonic notch performance is improved by 23 dB. Additionally, the LNA achieves a minimum noise figure of 3.1 dB, third order input intercept point ( I I P 3 ) of 0.5 dBm, input reflection (S 11 ) below −10 dB from 1.8 GHz–2.3 GHz operational frequency range, and consumed 19 mW of power from a 1.2 V supply.

The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology

The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.

Small-signal and noise GaAs pHEMT modeling for low noise amplifier design

Small-signal and noise GaAs pHEMT modeling techniques that include analytical extraction followed by optimization are demonstrated. The following measurement processing steps were carried out before the parameter extraction: de-embedding, data smoothing and selecting the bias mode appropriate for the extraction of parasitic resistances and inductances. A low-noise amplifier operating in 5G frequency band was designed using the resulting model. A comparison between simulation and measurements of noise factor and S-parameters of the obtained low-noise amplifier is presented.

IMPROVED PERFORMANCE OF LNA USING HIGH QUALITY FACTOR PGS ON-CHIP SPIRAL INDUCTORS

This paper presents a detailed study of on-chip spiral inductors with patterned ground shield (PGS) inserted between the spiral inductorand the silicon substrate. This new design has been implemented in source degeneration cascode lownoise amplifier (LNA) circuit to show how the PGS inductors improve the performance of the circuit. An operation in 1.8V supply voltage, source degeneration cascode LNA structure was studied with both technology and PGS inductors. In this paper, the Agilent ADS (Advanced Design System) simulation software and TSMC 0.18μm CMOS process parameters were adopted to achieve the low-cost characteristics and high integration to fit the performance of 2.4 GHz LNA design under IEEE 802.11a specification.According to the co-simulation results, the forward gain (S21) improved from 13.432 to 21.474 dB, and the (S12)is below the typical value of -15dB. The input impedance (S11) and the output impedance (S22) also represented good performance. In addition, the minimum noise figure was quite good. Thus, the LNA circuit with PGS inductorswas better in the availability and the possibility of 802.11a specification.

A Four-Channel CMOS Front-End for Interference-Robust GNSS Receiver

A four-channel receiver front-end is designed and implemented for interference- and jamming-robust global navigation satellite system (GNSS) in a 0.18-μm CMOS technology. The front-end consists of four identical RF-to-IF signal paths including low-noise amplifiers (LNAs), mixers and IF amplifiers. In addition, it also includes a phase-locked loop (PLL), which synthesizes the local oscillator (LO) signal, and a serial peripheral interface (SPI) for parameter adjustment. To improve the interference and jamming robustness, a novel linearity improvement technology and LO duty cycle adjustment method are applied in LNA and mixer design, respectively. The receiver achieves a gain of 40 dB, an input-referred third-order intercept point (IIP3) of −8 dBm and a jammer-to-signal power ratio (JSR) of 72 dB under 1.8-V and 3.3-V supply, while occupying a 4 × 5 mm2 die area including the electrostatic discharge (ESD) I/O pads.

Design of C-band Low-noise Amplifier (LNA) Using E-pHEMT Device for Satellite Communication System

A low-noise amplifier (LNA) plays an indispensable role in a communication system for amplification purposes at the transceiver. LNA design in radio frequency (RF) circuits involve various key attributes, namely noise figure (NF), gain, and power consumption. This paper focuses on the design of a C-band LNA for satellite communication system with a centre frequency of 6 GHz using ATF-55143 enhancement-mode pseudomorphic high-electron-mobility transistor (E-pHEMT) technology. The LNA performance is augmented by adding inductors to the drain and gate of the ATF-55143 transistor. Smith chart impedance matching technique is implemented to foster a more precise matching for input and output of the LNA. In this work, the C-band LNA is biased at VDS of 2.7 V and IDS of 10 mA. Electromagnetic (EM) software is used to design and simulate the performance of the LNA circuit layout. Simulation results indicate NF of 2.66 dB and power gain (S21) of 12.29 dB. The LNA consumes 27 mW from a 3 V DC supply.

28 GHz Off-the-Shelf Low Noise Amplifier for 5G Baseband Wireless System

This paper presents the simulation and measured results of a Low Noise Amplifier (LNA) working at 28 GHz for the 5G wireless system. LNA is used to amplify the weak receiving signals in the RF receiver system. The 28 GHz (Ka-band) LNA is designed to work for 5G technology wireless system. Here a Fujitsu FHR02X transistor is used in the simulation process, where the one-stage LNA is adopting a common-source with source inductive degenerative topology.In the fabrication process, GaAs pHEMT MMIC HMC519LC4 LNA is mounted on the Rogers 4003C board (εr = 3.38 and δ = 0.0027)and tested using (PNA-X N5246A) Microwave Network Analyzer. The final LNA design in the simulation process achieves a power gain of 9.185 dB, input and output return losses of – 13.124 dB and – 15.455 dB respectively, and noise figure of 9.185 dB. Furthermore, the fabricated LNA achieves a power gain of 10.91 dB, input and output return losses of - 7.75 dB and - 22.13 dB respectively. Although the return loss (S11) value is higher than -10 dB, but the LNA still able to obtain gain more than 10 dB.Thesimulation and fabricated LNA have input return loss quite closed to the given value in the datasheet. Thus, the LNA transmission line has a good output matching design.

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

Design and analysis of CMOS RF receiver front-end of LNA for wireless applications

This article deals the design and analysis of CMOS RF receiver front-end with the optimization of single-stage and two-stage low noise amplifier (LNA) for wireless applications. The low noise, high gain and better linearity for 3–10 GHz ultra wideband (UWB) wireless applications realized in 45 nm CMOS technology. The novelty of a single-ended and cascaded CMOS LNA designs for multi-standard purposeful for reconfigurable applications. The proposed LNA espouse entire circuit simulations investigation of the results in the center frequency of 3.4GHz. The admirable power gain (S21) is 32.5 dB with high reverse isolation (S12) of<−43.2dB; the preferable noise figure (NF) obtained as 0.9 dB. The perfect matching of input-output impedance for stability has measured to significantly input-output reflection coefficients S11=−11.6dB,S22=−10.0dB respectively while consuming only 11.8 mW from a 1 V supply.

A novel design of UWB low noise amplifier for 2–10 GHz wireless sensor applications

The paper reports a novel design of low noise amplifier (LNA) by cascading common gate, common source and common drain stage technique. The cascaded architecture achieves 5–10 dB of noise figure and 8.7 dB of gain in the required frequency band. The common gate stage provides input match while output match is fetched using common drain stage. The input/output match of below −20 dB/-10 dB is attained here. The reverse isolation is below −90dB. The 1-dB compression point and third intercept point (IIP3) is reported to be −27 dBm and 4.3 dBm at 7.7 GHz. The design is tested with the supplied voltage of 1 V. The proposed design is implemented using Cadence virtuoso analog and digital design environment in 90 nm CMOS technology.

An X/Ku Dual-Band Switch-Free Reconfigurable GaAs LNA MMIC Based on Coupled Line

This article presents an X/Ku dual-band switch-free reconfigurable GaAs low-noise amplifier (LNA) realized by inter-stage and output-stage coupled lines. This article is the first switch-free reconfigurable LNA design in the coupled lines structure. After amplified by the broadband drive stage, the input signal is divided into two parallel single-band stages (consists of a high-band stage and a low-band stage) by the proposed inter-stage coupled line. Two split-band signals are combined by the proposed output-stage coupled line into the output port after amplified by the single-band stages. The proposed coupled lines are also included in LNA matching networks. Dual-band operation of the proposed reconfigurable LNA is achieved by turning off drain voltages of the unused single-band transistors. The reconfigurable LNA is designed in a 0.15-μm E-mode GaAs pHEMT process. The fabricated LNA features small-signal gains of 25-25.2/20.1-28 dB, noise figure (NF) of 1.28-1.41/1.23-1.51 dB, and output 1-dB compression point of 0.5-1.7/2.2-5 dBm over 8-10/12-20 GHz, while consuming 76/91 mA of dc current, with a size of 2.0 × 1.8 mm 2 .

Design of Cryogenic LNAs for High Linearity in Space Applications

This paper presents a 2 GHz low noise amplifier (LNA) implemented in 180 nm complementary metal oxide semiconductor (CMOS) technology designed for cryogenic temperatures as well as its measurement results at both room temperature and 77 K. A modified approach to classical LNA design has been adopted. The matching of the LNA has been performed by external discrete components such that S11 and S22 of the LNA between 2.025 and 2.12 GHz (designated for space communications) are below -10 dB at both 77 K and 297 K. At 77 K, the designed LNA achieves 18 dB gain, 35.4 K noise temperature, and +3 dBm IIP3. IIP3 performance of the LNA at cryogenic temperatures has been analyzed in particular, and the linearity improvement by using the proposed approach has been demonstrated. Moreover, the designed LNA was irradiated with 650 krad gamma radiation. Even though the LNA is not specifically radiation-hardened, no degradation on its performance has been observed.

Differential CMOS Low Noise Amplifier Design for Wireless Receivers

This article presents the differential CMOS-LNA design for wireless receiver at the frequency of 3.4GHz. This differential provides less noise figure (NF), high gain and good reverse isolation as well as good stability. The designed LNA is simulated with a 180 nanometers CMOS process in cadence virtuoso tool and simulate the results by using SpectreRF simulator. This LNA exhibits a NF of 0.7dB, a high voltage gain of 28dB, and good reverse isolation (S12) of -70dB. It produces an input and output reflection coefficient (S11) of -6.5dB and (S22) of -14dB, and it maintains good stability of Rollet factor Kf &gt; 1, and also alternate stability factor B1f &lt; 1, respectively.

Highly linear wide band low noise amplifiers: A literature review (2010–2018)

Wideband (WB) CMOS low noise amplifier (LNA) design requires linearity consideration for better performance across the entire band because the increase in the number of interferers put severe constraints on system linearity requirements. In this paper, a literature review is presented within academic papers published with good linearity results on WB LNA between 2010 and 2018. Results of sample LNA designs are discussed with emphasis on bandwidth, noise figure (NF), gain and matching tradeoffs. This review provides useful insights on linearization techniques, the trade-offs consideration between the main parameters and also aids the creation of new ideas in this field. In addition, the designed LNAs have been compared with considering a new overall factor.

Simulation and Design of Low Noise Amplifier

A low-noise amplifier is an electronic amplifier that amplifies a very poor signal (in terms of its power) without significantly degrading its SNR. An amplifier increases the power of both the signal and the noise present at its input. A good LNA has a low Noise Figure as well as enough gain to boost the signal thereby does the work required of it. This paper proposes a LNA designed with ATF-21170 to operate in 2.4 GHz with a maximum gain of 18.453 dB and minimum NF 1.346

Low Noise Amplifier Design of CMOS Inductorless with Noise Cancellation Technique

This article presents the Low Noise Amplifier (LNA) design of CMOS Inductorless with noise cancellation (NC) technique for portable wireless receivers. An Inductorless CMOS LNA for multi-standard wireless applications with less-area, single-chip is presented. This NC technique is used to cancel out the noise involvement in LNAs at the output of matching device. The proposed Inductorless CMOS LNA designed in a CMOS 45nm GPDK technology process. The simulated results within the frequency range of 1.04GHz-1.8GHz are considered here. The maximum gain has achieved 20dB @ 1.04GHz, 23dB @ 1.8GHz and a low NF of 1.2dB @ 1.04GHz, 0.6dB @ 1.8GHz. The input and output reflection coefficients are obtained as less than -10dB it is desirable value to fit in this LNA.

Technologies, Design, and Applications of Low-Noise Amplifiers at Millimetre-Wave: State-of-the-Art and Perspectives

An overview of applicable technologies and design solutions for monolithic microwave integrated circuit (MMIC) low-noise amplifiers (LNAs) operating at millimeter-wave are provided in this paper. The review starts with a brief description of the targeted applications and corresponding systems. Advanced technologies are presented highlighting potentials and drawbacks related to the considered possibilities. Design techniques, applicable to different requirements, are presented and analyzed. An LNA operating at V-band (59–66 GHz) is designed and tested following the presented guidelines, demonstrating state-of-the-art results in terms of noise figure (average NF &lt; 2 dB). A state-of-the-art table, reporting recent results available in open literature on this topic, is provided and examined, focusing on room temperature operation and performance in cryogenic environment. Finally, trends versus frequency and perspectives are outlined.

Low Noise Amplifier Design for IoT Wireless Communication Systems

In the era of Internet of Things (IoT), the Internet has evolved from a simple Internet function of web information access to intelligent functions of identification, position, monitoring, and management of things. Devices in the IoT must transmit data between the devices and equipment connecting to cloud. As a fog computing architecture is established proximally at the local ends of the IoT, the data transmission volume and transmission delay can be effectively reduced. IoT wireless communication is one of the essential items for complete data transmission between the devices and on-line equipment. This paper proposes the low noise amplifier (LNA) design that can be applied to the RF front-end receiver of a 2.45-GHz wireless communication system for IoT applications. The LNA is required to have characteristics of low noise factor and high signal gain in order to amplify weak signals received by the antenna. In this study, the design of 2.45-GHz LNA adopts an architecture of power-constrained simultaneous noise and input matching on the basis of the 0.18-μm CMOS process technology in order to achieve simultaneous noise and input matching at low power conditions. Both the architectures of push-pull and forward substrate bias are also utilized. The LNA demonstrates the characteristics of low noise factor, high gain, and good 1-dB gain compression. The LNA shows good potential for IoT wireless communication system applications.