Low-jitter Clock Research Articles

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.

Ultra-low jitter clock distribution for the trigger electronics of the New Small Wheel for the ATLAS experiment

The Large Hadron Collider (LHC) at CERN plans to have a series of upgrades to increase its instantaneous luminosity to 7.5 × 1034 cm−2 s−1. The increased luminosity drastically impacts the ATLAS trigger and readout data rates. The inner-most station of the ATLAS muon spectrometer, the so-called Small Wheels is being replaced with a New Small Wheel (NSW) system, consisting of Micromegas and small-strip Thin Gap Chambers (sTGC) detectors. The on-detector radiation levels required radiation tolerant electronics. The lower radiation levels on the rim of the NSW allowed utilizing commercial electronic chips, such as Field Programmable Gate Arrays (FPGAs), in the trigger chain of the sTGC detectors. Those FPGAs require an ultra-low jitter clock for the proper operation of their Gigabit transceivers (4.8 Gb/s serial links). The initial design was based on a clock provided by a radiation tolerant ASIC designed at CERN, but due to its intrinsic jitter and consequent marginal error rate on the transmission lines, a different approach had to be chosen. An additional clock source based on commercial jitter cleaners, fanout chips and optical transmitters driving dedicated fibers was built. The new scheme provides 64 low-jitter clocks (32 main and 32 redundant) from the radiation-protected area (USA15) to the trigger electronics over 60 m of OM3 fiber.

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Modeling and Analysis of a Frequency-Locked Loop Based on Two-Stage Ring Voltage-Controlled Oscillator

In this paper, an analytical model of a closed-loop frequency-locked loop (FLL) based on a two-stage voltage-controlled oscillator (VCO) is proposed. Switch capacitor technology is used to accelerate the conversion speed of the frequency-to-voltage converter for reducing the locking time. The VCO is reduced to the minimum two-stage delay ring structure for outputting high-frequency signals with less variation caused by process, voltage, and temperature drift. Based on the strategy that focuses on the optimization of the loop bandwidth, a low jitter GHz clock with a wide swing and a strong capacitive load driving ability is realized. The proposed FLL is implemented in TSMC 0.35 μm 3.3 V CMOS process. From the experimental results, the output frequency is ranged from 750 MHz to 1.27 GHz, and the RMS jitter of the output clock is less than 36 ps under 1.039 GHz. The generated low-jitter clock is suitable for GHz gating applications in single-photon detection.

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.

3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS

This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fsrms at a data rate of 25.78125 Gb/s.

A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.

12 Gbit/s three‐tap FFE half‐rate transmitter with low jitter clock buffering scheme

A 12 Gbit/s feed-forward equalisation (FFE) transmitter has been designed in 65 nm CMOS process. The three-tap/half-rate highspeed tap signal generation technique for the segmented FFE driver is presented. A clock buffer scheme to make the equivalent signal transition for each segmented unit contributes to a low jitter performance. The measurement results show 9.31 ps RMS jitter at 12 Gbit/s after equalisation and the horizontal eye-opening is 0.204 UI at 10 -12 BER. The prototype transmitter occupies 0.042 mm 2 and consumes 1.58 pJ/bit.

Study of low power front-ends for hybrid pixel detectors with sub-ns time tagging

Power consumption is always a concern in the design of readout chips for hybrid pixel detectors. The Timepix3 chip is capable of dealing with up to 80 Mhits/cm2/sec and tagging each hit within a time bin of 1.56 ns. At full speed the Timepix3 chip will consume 1.3 W. We consider how to reduce power consumption if hit rate and/or time stamp precision is not important. The analog power can be reduced by more than an order of magnitude with little impact on noise by reducing the bias current of the input transistor and increasing the return to zero time of the preamplifier. Digital power consumption might be ∼ 6× lower by reducing the clock frequency to 1 MHz from the nominal 40 MHz. Simulations and measurements are presented. In very low power mode Timepix3 could consume only ∼150 mW on 2 cm2. The new Timepix4 chip aims at time tagging within a bin of 200 psec. Propagation of a 5 GHz clock around the pixel matrix would be impractical. We present a novel architecture implementing a very low jitter clock to the full pixel matrix. A digital Delay Locked Loop is designed in which the delay chain is distributed along the two columns of each super-pixel with the phase comparator and control located at the base of the double column. The control system locks all super-pixels to the low jitter (<100 ps) global 40 MHz clock. Simulations show that this can be achieved with a power consumption of only 25 mW/cm2 while preserving high rate capability.

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

Implementation of low-noise power-efficient clock multipliers requires low-noise high-frequency reference clocks. This paper presents ways to generate such reference clocks at four times the frequency of a standard crystal oscillator (XO) output frequency. Using extensive digital correction techniques, a 216-MHz reference clock with an integrated jitter of 77fsrms is generated from a 54-MHz Pierce XO. A ring oscillator-based injection locking clock multiplier driven by the proposed quadrupler is used to demonstrate the efficacy of the quadrupler. Fabricated in a 65-nm CMOS process, the proposed clock multiplier occupies an active area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and achieves 366fsrms integrated jitter at 4.752-GHz output frequency while consuming 6.5-mW power from a 1.0-V supply of which 1.5 mW is consumed in the quadrupler.

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology

This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event upsets (SEUs). The circuit is designed for high-energy particle physics experiments for low-jitter clock generation and clock recovery. An optimal tuning strategy of the VCO is presented that minimizes the cross section and the SEU sensitivity of the oscillator. The circuit is processed in a 65-nm CMOS technology and has been irradiated with heavy ions with a linear energy transfer between 10 to 69.2 MeV.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. A comparison has been made with a conventional oscillator which proves a significant improvement in SEU sensitivity.

Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration

A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13- $\mu \text{m}$ CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc.

The integration of FPGA TDC inside White Rabbit node

White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

ABSTRACTThis paper presents a novel multi-levels time-to-digital converter (TDC) suitable for array architecture for the photon time-of-flight (TOF) measurement. A simple method was applied to solve the initial phase time mismatch caused by random occurrence of the TOF start signal. A low-jitter phase-locked loop (PLL) is adopted to provide excellent clocks to the TDC. The proposed PLL–TDC has a good differential nonlinearity (DNL) (±0.4 LSB) and integral nonlinearity (INL) (±0.5 LSB) due to the low-jitter clock and elimination of initial phase time mismatch. The circuit of the low-jitter PLL was implemented in TSMC 0.35 µm standard complementary metal oxide semiconductor (CMOS) process with 3.3 V supply voltage. The measured result of the low-jitter PLL and the simulated result of the TDC show the proposed 14-bit TDC can realize 1.0 ns time resolution and 16 µs maximum range with 125 MHz centre frequency. Under this given frequency, the time interval error (TIE) jitter is 7.8 ps(rms).

Design of Continuous-Time &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta \Sigma $&lt;/tex-math&gt; &lt;/inline-formula&gt; Modulators With Dual Switched-Capacitor Return-to-Zero DACs

Single-bit continuous-time sigma-delta modulators (CTDSMs) are overly sensitive to clock jitter when a non-return-to-zero (NRZ) feedback DAC is used. One way of addressing this problem is to use a DAC with an exponentially decaying pulse shape, realized using a switched capacitor (SC). Existing variants of the SC feedback DAC degrade linearity due to the high peak-to-average ratio of the feedback waveform and severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the dual switched-capacitor return-to-zero (Dual-SCRZ) DAC, which combines the low clock jitter sensitivity of a switched-capacitor DAC with the low peak-to-average ratio characteristic of NRZ feedback. Further, this DAC preserves the implicit anti-aliasing feature of the CTDSMs around all odd multiples of the sampling frequency. A single-bit CTDSMs that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at 256 MHz in a $0.18\;\mu\text{m}$ CMOS process, the modulator dissipates 14.8 mW from a 1.8 V supply.

Generation and Distribution of Josephson Junction Clock

One of the crucial factors in achieving high performance of superconducting integrated circuits, such as analog-to-digital converters (ADCs), is sampling using a high-frequency clock source with a low cycle-to-cycle jitter. As the superconductor ADC technology matures toward more complex designs for higher dynamic range performance, the need for synchronous clocking of multiple comparators continues to grow. Since high-frequency external clock sources are expensive and make a significant contribution to the heat load of the system, a high-frequency and low-jitter on-chip clock source using long Josephson junction (LJJ) is considered the preferred long-term solution. Toward that end, we are working on improving an on-chip 110-GHz clock source based on an unshunted LJJ in annular geometry. Minimizing the additional jitter added by each fan-out of the clock signal is the effort's goal. For synchronous clocking of up to three comparators, we compare clock distribution using superconducting passive transmission lines and a new approach using novel active transmission lines. We also introduce a method of synchronizing LJJ clock source with an external stable oscillator by injection locking.

Clock auto-synchronization method for BESIII ETOF upgrade**Supported by National Natural Science Foundation of China (10979003, 11005107), CAS Center for Excellence in Particle Physics (CCEPP)

An automatic clock synchronization method implemented in a field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing Spectrometer (BESIII). In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned, the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square (RMS), but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.

An 85mW 14-bit 150MS/s pipelined ADC with a merged first and second MDAC

A low-power 14-bit 150MS/s analog-to-digital converter (ADC) is presented for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the performance. The prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 mW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology

This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically injection-locked PLL (SILPLL) with auto-adjust injection timing is employed to provide low jitter clock source. A power-efficient 2-tap feed-forward equalizer (FFE) based on open loop 1-UI delay generation is implemented as the transmitter equalizer. Fabricated in 65 nm CMOS technology, the transmitter running at 40 Gb/s consumes 80 mW power under 1.2 V supply. The PLL RMS jitter is 98 fs integrating from 100 Hz to 100 MHz and the total jitter of 40 Gb/s eye diagram is 6.7 ps for 1e-12 BER.

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10 -9 . The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm $^{2}$ per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s.