Low-jitter Clock Research Articles

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm2, and consumes 518 mW at 1.8 V supply.

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order $\Delta\Sigma$ Modulator in 90-nm CMOS

A 10 Gb/s receiver with a digital CDR uses a track-and-hold-type linear phase detector (LPD) and charge-redistribution first-order ΔΣ modulator. It has low quantization error and high loop bandwidth due to the use of the LPD and maintains the advantages of a digital CDR such as low power consumption, small area, fast locking time, and low-jitter recovery clock because no internal VCO is needed. The CDR tracking bandwidth is 20 MHz and high-frequency jitter tolerance is 0.42 UIpp at 10-12 BER. Power consumption of LPD is 2.6 mW while the entire receiver consumes 65 mW.

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm2 and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System

Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35 μm CMOS process. Furthermore, these techniques are successfully verified in 14 ps circuit resolution and a 500 * 750 μm chip area for the 100―400 MHz measurement range.

A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-.MU.m CMOS

This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13µm CMOS process achieves 105MHz to 225MHz of clock frequency while consuming 4.2mW from 1.2V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8ps and 0.031% at 105MHz, respectively.

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning

A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis of the loop stability is provided. The frequency synthesizer occupies an active area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply. The measured rms jitter is 3.5 ps for a 229.5-MHz output clock.

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kOmega and a differential output swing of 520 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> with for input spanning from to . The measured integrated input-referred noise is 3.3muA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> . The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 PRBS input, the recovered clock jitter is and 0.7ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> . The retimed data exhibits 13.3 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> jitter with BER . Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply

A sampling ADC data acquisition system for positron emission tomography

A data acquisition system for a positron emission tomograph (PET) based on avalanche photodiode (APD) readout of lutetium oxyorthosilicate (LSO) scintillator crystals is presented. The analog data of each APD are read out by fast analog to digital converters (ADCs) and processed within field programmable gate arrays (FPGAs). The ADCs are continuously sampling with a 80 MHz, low jitter clock, which is synchronous for the whole detector. The main tasks of the FPGAs are pulse detection and extraction of signal timing information from the digitized data stream. The detected signal pulse data are therefore compared to a predefined set of pulse shapes with known phase shifts with respect to the sample clock. By searching for the best match within this calibration set, a precise start time information for the signal pulse can be determined. The calculated time values are then transmitted from the ADC cards via fiber optic links to multiplexer modules which combine the different data streams and can also perform further processing like search for coincident events. Finally, the preprocessed detector data are transmitted from the multiplexers to PCI cards in the image reconstruction computers by gigabit optical links

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS

We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm/sup 2/. A new architecture is proposed which improves the authors' previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.

Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination

We propose and demonstrate a Gaussian frequency-shift keying and Gaussian minimum-shift keying (GMSK) pulse-shape filtering for wireless RF transmitters with an arbitrary reference frequency. The filter is software controlled to work in a multistandard radio. Spurs, which are due to the frequency injection pulling, in cases when the reference harmonics are close enough to the oscillating frequency, are avoided by means of retiming the reference clock by the RF oscillator. Baseband clock for the pulse-shape filtering is derived through a simple fractional-N division of the reference frequency. This saves area and power since it is no longer required to create a low-jitter clock for baseband symbol generation and modulating data. It is especially advantageous when the available reference frequency is not an integer multiple of the symbol rate. The presented transmitter is realized without any explicit analog filtering and is part of a commercial single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. We demonstrate the software programming capability through an experimental GMSK modulation for the global system for mobile communication.

Hybrid photonic analog-to-digital conversion using superconducting electronics

A hybrid analog-to-digital converter is described that uses photonic waveform sampling coupled with superconducting electronics for quantization and conversion to a binary format. The architecture scheme exploits extremely low clock jitter, amplitude stability, and a picosecond sampling aperture from the photonic system and magnetic flux quantization and high-speed digital logic in the superconducting system. The operational speed of the conversion is primarily limited by the maximum speed of the superconducting logic elements.

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.

A fully integrated low-power low-jitter clock synthesizer with 1.2 GHz tuning range in SiGe:C BiCMOS

We present an integrated clock synthesizer in SiGe:C BiCMOS technology. The synthesizer is aimed at low-jitter applications requiring a wide continuous frequency range at low power consumption. It uses an nMOS VCO with an LC tank and differential tuning followed by a bipolar dual-modulus prescaler. The circuit draws 28 mA from a 2.5 V supply. The measured rms output jitter of the PLL was below 2 ps over the whole tuning range from 4.9 to 6.1 GHz.

A low-jitter phase-interpolation DDS using dual-slope integration

In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the phase accumulator to provide positive-slope integration on an integration capacitor in the first phase, and then performs negative-slope integration operation on the same integration capacitor in the second phase. By using dual-slope integration on a single capacitor, the delay time error caused by capacitance error can be avoided and the die size can be reduced in circuit implementation. Therefore, the proposed DDS without ROM tables can achieve a low-jitter clock output due to generating the more precise delay time.