Low Output Impedance Research Articles

Design and Experimental Evaluation of Quadrature Oscillator Employing Single FB–VDBA

Abstract This paper presents an attractive and a new voltage-mode quadrature oscillator using a single Fully Balanced-Voltage Differencing Buffer Amplifier (FB-VDBA) as the active element. The circuit structure is very simple, consisting of merely one FB-VDBA, one resistor and two capacitors. The circuit is implemented using the commonly available OPA860 which results in low output impedance and high current drive capability. The proposed circuit also has a suitable architecture for IC production. Experimental results which are matched well with the theoretical assumptions are given.

Design and Analysis of an Adaptively Biased Low-Dropout Regulator Using Enhanced Current Mirror Buffer

This paper presents an adaptively biased low-dropout regulator using an enhanced current mirror (ECM) buffer for effectively driving the gate of the PMOS power transistor. The proposed ECM buffer offers very low output impedance, which pushes out the pole at the gate of the PMOS power transistor to improve the stability. At the same time, it offers a symmetric pull-up/down slew rate to enhance the speed of the buffer, whenever the regulator is under large signal operation during the load transient. Moreover, the ECM buffer is modified to develop the regulator topology without introducing an error amplifier as a separate independent stage. It helps to minimize the overall quiescent current consumption at low-load condition and makes frequency compensation easier. Finally, the speed of the adaptive bias loop is increased by avoiding the highly capacitive gate node of the PMOS power transistor. A comprehensive small-signal analysis of the proposed regulator is also carried out for a clear understanding of the stability of each loop considering the interaction of the other loop. The regulator is implemented in a 0.18- $\mu$ m CMOS technology with a quiescent current of 900 nA. A maximum transient output voltage variation of 2.1% is observed with $C_{o}$ = 470 nF.

A Voltage-Mode Universal Biquadratic Filter Using DDCCTA

This paper presents a new voltage-mode (VM) universal biquadratic filter using differential difference current conveyor transconductance amplifier (DDCCTA) as an active element. The circuit employs one DDCCTA, two floating resistors and two floating capacitors which can realize five biquadratic filters, namely low-pass (LP), band-pass (BP), band-stop (BS), high-pass (HP) and all-pass (AP) into one single topology. For realizing these filtering functions, passive component-matching conditions, inverting-type and/or doubling-input signal requirements and changing circuit configuration are absent. The natural angular frequency and quality factor of the filter can be orthogonally controlled deliberately. The VM biquadratic filter using grounded passive components with high-input and low-output impedances can be obtained by adding an additional DDCCTA or differential difference current conveyor (DDCC). The simulation results with 0.5[Formula: see text][Formula: see text]m CMOS process from MIETEC are given to confirm the theoretical predictions and the experimental results are also included to verify the workability of the proposed structure.

A First-Order Fully Cascadable Current-Mode Universal Filter Composed of Dual Output CCIIs and a Grounded Capacitor

In this paper, a new first-order current-mode (CM) universal filter employing two dual output second-generation current conveyors (DO-CCIIs), one resistor and a grounded capacitor is proposed. The proposed filter has low input and high output impedances; thus, it can be easily connected with other CM circuits. It can simultaneously realize first-order low-pass (LP) and all-pass (AP) responses and can provide high-pass (HP) response with interconnection of LP and AP responses. It can be tuned electronically by replacing with dual output second-generation current controlled conveyors (DO-CCCIIs) instead of DO-CCIIs and removing the resistor. It has only a resistor but no capacitor connected in series to X terminal of DO-CCII; accordingly, it can be operated at high frequencies. Also, it does not need any critical passive component matching conditions and cancellation constraints. A number of simulation results based on SPICE program are included to exhibit performance, workability and effectiveness of the proposed filter configuration.

A new electronically tunable first-order all-pass filter using only three NMOS transistors and a capacitor

In this paper, a new first-order voltage-mode (VM) all-pass filter that consists of only three NMOS transistors and a capacitor is proposed. The resonance frequency of the proposed circuit can be tuned electronically by a control current. It has high input impedance; thus, it can be easily cascaded with other VM circuits. Furthermore, it does not require any critical passive component matching conditions. Nevertheless, it does not have low output impedance. Although a floating capacitor is used in the proposed circuit, it can be easily realized with today’s technologies. Ideal and nonideality analyses are performed for the proposed circuit. The behavior of the filter is verified by a number of SPICE simulations and an experimental test. The total harmonic distortion variations of the proposed circuit are found low enough.

Double closed-loop cascade control for lower limb exoskeleton with elastic actuation

Unlike traditional rigid actuators, the significant features of Series Elastic Actuator (SEA) are stable torque control, lower output impedance, impact resistance and energy storage. Recently, SEA has been applied in many exoskeletons. In such applications, a key issue is how to realize the human-exoskeleton movement coordination. In this paper, double closed-loop cascade control for lower limb exoskeleton with SEA is proposed. This control method consists of inner SEA torque loop and outer contact force loop. Utilizing the SEA torque control with a motor velocity loop, actuation performances of SEA are analyzed. An integrated exoskeleton control system is designed, in which joint angles are calculated by internal encoders and resolvers and contact forces are gathered by external pressure sensors. The double closed-loop cascade control model is established based on the feedback signals of internal and external sensor. Movement experiments are accomplished in our prototype of lower limb exoskeleton. Preliminary results indicate the exoskeleton movements with pilot can be realized stably by utilizing this double closed-loop cascade control method. Feasibility of the SEA in our exoskeleton robot and effectiveness of the control method are verified.

Low Voltage High Output Impedance Bulk-Driven Quasi-Floating Gate Self-Biased High-Swing Cascode Current Mirror

A low voltage self-biased high-swing cascode current mirror using bulk-driven quasi-floating gate MOSFET is proposed in this paper. The proposed current mirror bandwidth and especially the output impedance show a significant improvement compared to prior arts. The current mirror presented is designed using bulk-driven and bulk-driven quasi-floating gate N-channel MOS transistors, which helped it to operate at very low supply voltage of $${\pm }0.2\,\hbox {V}$$±0.2V. To achieve high output resistance, the current mirror uses regulated cascode stage followed by super cascode architecture. The small-signal analysis carried out proves the improvement achieved by proposed current mirror. The current mirror circuit operates well for input current ranging from 0 to $$250\,{\upmu }\mathrm{A}$$250μA with good linearity and shows the bandwidth of 285 MHz. The input and output resistances are found as $$240\,\Omega $$240Ω and $$19.5\,\hbox {G}\Omega $$19.5GΩ, respectively. Further, the THD analysis and Monte Carlo simulations carried prove the robustness of proposed current mirror. The complete analysis is done using HSpice on UMC $$0.18\,\upmu \mathrm{m}$$0.18μm technology.

A CMOS frontend chip for implantable neural recording with wide voltage supply range**Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a −3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip.

Human–Robot Interaction Control of Rehabilitation Robots With Series Elastic Actuators

Rehabilitation robots, by necessity, have direct physical interaction with humans. Physical interaction affects the controlled variables and may even cause system instability. Thus, human–robot interaction control design is critical in rehabilitation robotics research. This paper presents an interaction control strategy for a gait rehabilitation robot. The robot is driven by a novel compact series elastic actuator, which provides intrinsic compliance and backdrivablility for safe human–robot interaction. The control design is based on the actuator model with consideration of interaction dynamics. It consists mainly of human interaction compensation, friction compensation, and is enhanced with a disturbance observer. Such a control scheme enables the robot to achieve low output impedance when operating in human-in-charge mode and achieve accurate force tracking when operating in force control mode. Due to the direct physical interaction with humans, the controller design must also meet the stability requirement. A theoretical proof is provided to show the guaranteed stability of the closed-loop system under the proposed controller. The proposed design is verified with an ankle robot in walking experiments. The results can be readily extended to other rehabilitation and assistive robots driven with compliant actuators without much difficulty.

High Performance Voltage-Mode Tunable All-Pass Section

This paper presents a voltage-mode (VM) tunable all-pass section, employing a grounded capacitor and a newly introduced current conveyor with an extra X stage. The proposed all-pass filter uses grounded capacitor as the only passive component and benefits from high input and low output impedance. The proposed circuit exhibits eight performance features without trade-offs, as compared to carefully chosen 25 published works. The functionality of the proposed element is verified through PSPICE simulation using 0.25-μm process parameters. An application of second order is also incorporated.

A New Voltage-Mode Multifunctional Filter Using Only Two Voltage Followers and a Minimum Number of Passive Elements

A new voltage-mode (VM) multifunctional filter using only two voltage followers (VFs), two resistors and two capacitors is proposed. The proposed filter with two inputs and two outputs can provide low-pass (LP) and high-pass (HP) responses. It does not need any critical passive component matching constraints. Additionally, it has low output impedances, low power dissipation and adequately low THD values. However, it does not have high input impedances; accordingly, it requires an extra VF to obtain high input impedance. A number of time domain and frequency domain simulations and experimental tests are performed to verify the claimed theory.

A high linearity current mode second IF CMOS mixer for a DRM/DAB receiver**Project supported by the National Natural Science Foundation of China (No. 61306069), and the National High Technology Research and Development Program of China (No. 2011AA010301).

A passive current switch mixer was designed for the second IF down-conversion in a DRM/DAB receiver. The circuit consists of an input transconductance stage, a passive current switching stage, and a current amplifier stage. The input transconductance stage employs a self-biasing current reusing technique, with a resistor shunt feedback to increase the gain and output impedance. A dynamic bias technique is used in the switching stage to ensure the stability of the overdrive voltage versus the PVT variations. A current shunt feedback is introduced to the conventional low-voltage second-generation fully balanced multi-output current converter (FBMOCCII), which provides very low input impedance and high output impedance. With the circuit working in current mode, the linearity is effectively improved with low supply voltages. Especially, the transimpedance stage can be removed, which simplifies the design considerably. The design is verified with a SMIC 0.18 μm RF CMOS process. The measurement results show that the voltage conversation gain is 1.407 dB, the NF is 16.22 dB, and the IIP3 is 4.5 dBm, respectively. The current consumption is 9.30 mA with a supply voltage of 1.8 V. This exhibits a good compromise among the gain, noise, and linearity for the second IF mixer in DRM/DAB receivers.

A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.

Single Active Element Based Cascadable Band-Pass Filters for Low-Q Applications

The paper presents new single active element based second order band pass filters. The new circuits use single dual-X current conveyor with buffered output and five passive components. The proposed circuits enjoy the features of high input impedance and low output impedance, which are desirable features for voltage-mode circuits. Circuit operation at high frequencies are verified along with non-ideality and parasitic study. The Monte Carlo analysis is also done which justify good sensitivity performances of the proposed circuits. Routh–Hurwitz's stability test is performed to verify the stability of the proposed circuits. For showing the integration aspect, resistorless band-pass filters are also realized. The proposed low-Q filters are useful for cascading. The feature of cascadability is further utilized by showing an application of fourth-order band-pass filter. The performances of the proposed circuits are depicted through Personal Simulation Program with Integrated Circuit Emphasis (PSPICE) simulations, which show good agreement to theoretical applications. The new circuits are expected to enhance the already existing knowledge on the subject.

Linear Serial Elastic Hydraulic Actuator: Digital Prototyping and Force Control

In aggressive environments for humans, such as those present in the offshore industry, the main alternative is to replace human labor by remotely controlled robots, and some cases completely autonomous robots. The environment affects directly on robots tasks. When a robot works in a structured environment, its automation is easier since the environment can be modeled by dynamics equations. However if the environment is non-structured this modeling is quite difficult and presents a high computational effort. To overcome this difficult, over the years series elastic actuator (SEA) has been applied in non-structured environments. Actuators of the mechanical systems are always rigidly connected to the load to be moved. This can be observed in the hydraulic systems of agricultural, highway construction and mining equipment and in elevation and cargo transportation, among others. Unlike rigid actuators, a SEA contains an elastic element in series with the mechanical energy source. Such an elastic element gives SEA's several unique properties compared to rigid actuators, including tolerance to impact loads, low mechanical output impedance, passive mechanical energy storage, and increased peak power output. However it is not trivial to select the correct spring for the system. The spring has to be able to support the loads, but the spring cannot be too stiff, otherwise system impedance will be high. Iterative methods are needed to select the spring, which fits in impedance and bandwidth parameters. The resonance frequency is another issue for SEAs. This paper describes an entire digital prototyping of a linear serial elastic hydraulic actuator. It is done a digital prototyping of a tubular actuator design, which encapsulates the mechanical and electrical components and sensors. The digital prototype dimensions, mass and inertia properties are used to build the dynamic model for simulations and implementation of a controller. Moreover the methodology adopted results in a good response actuator with a compact and high force design

Transmission of Larger Amplitude Ultrasound with SiC Transistor Pulser for Subharmonic Signal Measurements at Closed Cracks

With measurements using the Subharmonic Phased Array for Crack Evaluation system, transmission of large-amplitude ultrasound is required to generate subharmonics near closed cracks. We designed a new pulser using a SiC transistor making larger currents available with low output impedance to generate large-amplitude signals. We report on the efficacies of the pulser in comparison with a conventional pulser. We investigated combinations of excitations from several transducers and the two pulsers by measuring signal amplitude, effective voltage, and electric current for each transducer. By applying larger electric currents, larger excitation amplitudes were produced, even when the capacitance oftransducer was larger.

High performance folded cascode OTA using positive feedback and recycling structure

In this paper, a new technique for enhancing the transconductance and low frequency output impedance of recycling folded cascode amplifiers is presented. These improvements were achieved by using a positive feedback and upgrading the recycling structure. The new structure benifits from better transconductance, slew rate, and DC gain in comparison to conventional folded cascode (FC) amplifier. Moreover, the input referred noise and input offset are reduced and the phase-margin is improved. The improved amplifier is simulated in 0.18 µm CMOS technology, demonstrates a DC gain enhancement of 16.4 dB as well as 117.5 MHz increase in gain bandwidth compared with conventional FC configuration. The amplifier consumes 360 µW @ 1.2 V which makes it appropriate for low-voltage applications.

New Squaring and Square-rooting Circuits Using Cdba

One new squaring and two new square-rooting circuits based on CDBAs have been introduced. The new squarer circuit consists of a CDBA, two NMOS transistors and one resistor. On the other hand, the first square-rooting circuit consists of two CDBAs, two NMOS transistors while the second square- rooting circuit consists of only a single CDBA, two NMOS transistors and two PMOS transistors. The proposed circuits exhibit wide input voltage range, very small error and offer low output impedance to facilitate easy cascading without requiring additional buffers. PSPICE simulation results are included which confirm the practical workability of the new circuits.

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor. The AEs amplify the weak EEG signals, while their low output impedance suppresses cable-motion artifacts and 50/60 Hz mains interference. A common-mode feed-forward (CMFF) scheme boosts the CMRR of the AE pairs by 25 dB. The BE post-processes and digitizes the analog outputs of the AEs, it also can configure them via a single-wire pulse width modulation (PWM) protocol. Together, the AEs and BE are capable of recording 8-channel EEG and ETI signals. With EEG recording enabled, ETIs of up to 60 kΩ can be measured, which increases to 550 kΩ when EEG recording is disabled. Each EEG channel has a 1.2 GΩ input impedance (at 20 Hz), 1.75 μVrms (0.5-100 Hz) input-referred noise, 84 dB CMRR and ±250 mV electrode offset rejection capability. The EEG acquisition system was implemented in a standard 0.18 μm CMOS process, and dissipates less than 700 μW from a 1.8 V supply.

Design of a New CMOS TRA

A new complementary metal oxide semiconductor transresistance amplifier that is very suitable for high-gain and low-voltage analog application is presented in this paper presents. The designed transresistance amplifier features common-source and gain-boosting topology to improve the gain of the transresistance amplifiers. The complementary metal oxide semiconductor transresistance amplifier provides low input and output impedances, which are required for the design of I-V analog circuits. Conventional common-drain, current-mirror, and common-gate transresistance amplifiers are analyzed through small signal analysis and simulation, and the results are compared with those of the proposed transresistance amplifiers. HSPICE simulation confirmed that the proposed transresistance amplifier has a gain of 83.9 dBΩ and provides higher gain by up to 30.1dBΩ compared to the other transresistance amplifiers.