A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process

Abstract

In this paper, we present a single-bit clock-less asynchronous delta–sigma modulator (ADSM) operating at just 0.25 V power supply. Several circuit approaches were employed to enable such low-voltage operation and maintain high performance. One approach involved utilizing bulk-driven transistors in subthreshold region with transconductance-enhancement topology. Another approach was to employ distributed transistor layout structure to mitigate the effect of low output impedance due to halo drain implants employed in today’s digital CMOS process. The ADSM achieved a characteristic center frequency of 630 Hz. It had an effective signal-to-noise-plus-distortion ratio (SNDR) of 58 dB or effective number of bits (ENOB) 9 b and just 28-nW power dissipation. A detailed analytical model capturing the effect of nonidealities of the individual circuit components is also presented for the first time with a close agreement with experimental results.