Low Gate Leakage Current Research Articles

High-temperature operation of Al2O3/Ga2O3 bi-layer gate stack GaN MOS-HEMT up to 450 °C with suppressed gate leakage

Abstract In this work, we report the reduced gate leakage current by using aluminum oxide (Al2O3) and gallium oxide (Ga2O3) as a bi-layer gate stack for GaN MOS-HEMT on a silicon substrate up to 450 °C. The bi-layer gate stack MOS-HEMTs suppressed the gate leakage by more than four orders of magnitude compared to only Al2O3-based GaN MOS-HEMT at 450 °C. The low gate leakage current is attributed to the reduced oxygen vacancies present in the Ga2O3 layer, which effectively impede the conduction path of the Poole-Frenkel emission at high temperatures, thereby enhancing the overall performance of GaN HEMTs.

Nonresonant Terahertz Detector Based on Improved N‐Polar AlGaN/GaN Plasma Wave High‐Electron‐Mobility Transistors

The THz photoresponse of four different structures of N‐ and Ga‐polar AlGaN/GaN plasma wave high‐electron‐mobility transistors (HEMTs) has been comparatively investigated. Based on these results, an improved N‐polar plasma wave HEMT detector is proposed: an AlGaN cap layer is introduced in the standard N‐polar HEMT, so as to obtain a lower gate leakage current, thus improving the operating characteristics of plasma wave HEMT. The results show that the responsivity of the improved N‐polar HEMT obtains a significant improvement and as the Al component of AlGaN cap layer increases, the noise equivalent power of the improved N‐polar HEMT has also been optimized.

Reduction of interface defects in gate-recessed GaN HEMTs by neutral beam etching

This study investigates and compares the impact of different etching techniques on the fabrication of GaN high electron mobility transistors (HEMTs) between the inductively coupled plasma reactive ion etching (ICP-RIE) and the neutral beam etching (NBE) for the gate recess. By conducting direct current analysis, it was found that devices manufactured using the NBE exhibited superior electrical performance as compared with those produced using the ICP-RIE. These enhanced electrical characteristics include a transconductance of up to 100.4 mS/mm, a threshold voltage (Vth) of −2.3 V, an on/off current ratio of 1.1 × 109, a subthreshold swing (S.S.) of 99.63 mV/dec, and a remarkably low gate leakage current. Additionally, we noted varying degrees of hysteresis in the I–V characteristics were related to process disparities possibly leading to interface defects. Multi-frequency capacitance-voltage (C–V) measurements were used to identify the interface defects at the oxide/AlGaN interface of the gate. The results revealed that devices fabricated using the NBE exhibited a lower interface defect density as compared with those fabricated using the ICP-RIE, thereby elucidating the reduced hysteresis observed in the I–V characteristics. These findings indicated the significant advantages of the NBE process in the fabrication of GaN HEMTs.

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer

In this paper, we explore the electrical characteristics of high-electron-mobility transistors (HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor (MIS) structure. The high-resistance tantalum nitride (TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10−7 mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Control of Surface Chemistry in Recess Etching toward Normally Off GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

Reducing off‐state and gate leakage current is crucial in the development of metal–insulator–semiconductor high‐electron‐mobility transistors (MIS‐HEMTs). This work reports interface engineering in the gate recess region through low‐damage digital etching during the fabrication of normally off GaN MIS‐HEMTs. Conventional plasma etching leads to a reduction of the N/(Al+Ga) ratio, but this value recovers to almost 1 with optimized oxidation condition during digital etching, suggesting a reduction of the Al/Ga dangling bonds based on the proposed technique. GaN MIS‐HEMTs with digital etching exhibits a threshold voltage of 1.0 V at 1 μA mm−1, a high ON/OFF current ratio of 1010, a gate breakdown voltage of 22 V, and a low gate leakage current of 10−8 mA mm−1.

Tunable EOT Scaling Down to 0. 55 nm for HfO2-Based Gate-Stacks on Ge Substrate by In Situ H2 Plasma Treatment

Abstract We propose a continuous fabrication method for HfO2-based gate stacks on a Ge bulk p-type metal–oxide–semiconductor capacitor (pMOSCAP) with HfGeOx interfacial layer by H2 plasma treatment through in situ plasma-enhanced atomic layer deposition. The electrical characteristics showed that the proper hydrogen plasma treatment could obtain an aggressively scaled equivalent oxide thickness of approximately 0.55 nm and a relatively low gate leakage current of 8 × 10-4 A/cm2 under PMA 500C.

High-κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low-Power Steep-Switching Computing Devices.

Herein, a high-quality gate stack (native HfO2 formed on 2D HfSe2) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density (Dit ≈ 5 × 1010 cm-2 eV-1). The chemically converted HfO2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10-3 A cm-2) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high-quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe2 layer without a substitution energy barrier, allowing layer-by-layer oxidation to proceed. The field-effect-transistor-fabricated HfO2/HfSe2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec-1 (over four orders of IDS) at room temperature (300 K), along with a high Ion/Ioff ratio of ≈108 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO2/HfSe2 gate stack and channel structures, an impact ionization field-effect transistor is fabricated that exhibits n-type steep-switching characteristics with a SS value of 3.43 mV dec-1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post-Si semiconducting devices for future energy-efficient data-centric computing electronics.

Gate leakage suppression of normally-OFF diamond FET by employing MOS-MES hybrid gate structure

Normally-off filed-effect transistors (FETs) are critical for logical circuit and switch systems. However, the presence of two-dimensional holes in hydrogen-terminated diamond (CH diamond) makes most of regular CH diamond MOSFETs normally-ON operation, leading to energy loss. Metal-semiconductor (MES) FETs with Schottky gate are a good way to achieve normally-off CH diamond FETs, but have the disadvantage of high gate leakage current. In this work, a MOS-MES hybrid gate diamond FET with normally-off operation and low gate leakage current was fabricated by adding nanoparticles Al2O3 (nano-Al2O3) between Al/C-H diamond interface. The MES formed by Al/C-H diamond plays the role of realizing normally-off operation, and the MOS of Al/nano-Al2O3/C-H diamond is used to lower the gate leakage current. 100 % of hybrid gate devices displayed normally-off operation with threshold voltages ranging from −0.2 V to −1.2 V, as well as the gate leakage current is 103-106-fold lower than that of FET without nano-Al2O3. The hybrid gate structure is poised to become a part of the FET community.

Design and Comparative Analysis of Silicon and GaAs MOSFET for Low Power Applications

The demand for low power consumption in modern electronic devices has led to the development of various technologies, including usage of different materials such as Si and GaAs. In this paper, we present a design and comparative analysis of Si and GaAs MOSFETs for low power applications. The analysis includes the electrical characteristics, performance parameters, and power consumption of both devices. The Si MOSFET and GaAs MOSFET are simulated and analyzed using TCAD tools, and the results are compared. The simulation results show that the GaAs MOSFET has a higher transconductance (gm) compared to the Si MOSFET. However, the Si MOSFET has a lower gate leakage current (Ig) and lower power consumption at low operating frequencies. We also investigate the effect of scaling on the performance and power consumption of both MOSFETs. The results show that scaling improves the performance of both devices, but the power consumption increases as the device dimensions are reduced. The comparative analysis of Si and GaAs MOSFETs for low power applications provides useful insights into the selection of suitable MOSFET technology for specific applications. The results show that both Si and GaAs MOSFETs have their advantages and disadvantages, and the choice depends on the application requirements.

Improved breakdown voltage mechanism in AlGaN/GaN HEMT for RF/Microwave applications: Design and physical insights of dual field plate

This work investigated and proposed the source–gate dual field plate (SG-FP) AlGaN/GaN HEMT for different gate-to-drain drift distances with a fixed gate length of 0.25 μm using ATLAS-TCAD. The increment in the GaN buffer thickness and gate-to-drain drift distance with the variation in the field plate length improves the device performance and breakdown voltages by maintaining the impact ionization mechanism. The breakdown voltage behavior, physical insights of electric field contour, impact generation rate, and potential profile intricacies of source field plate (S-FP), gate field plate (G-FP), and dual field plate (SG-FP) are illustrated. The proposed source–gate dual field plate (SG-FP) with the SiN passivation interfacial layer, SiO2, thicker GaN buffer, and extended gate-to-source drift region is best suited for optimal performance in high breakdown voltage, with optimum cut-off frequency and low gate-leakage current. The proposed dual field plate AlGaN/GaN device with the source field plate (LS-FP = 4 μm), gate field plate (LG-FP = 2 μm), the AlGaN buffer thickness of 3.697 μm, and gate-to-drain drift distance of 8 μm show the highest breakdown voltage of 562 V with the optimum frequency of 8.861 GHz. Finally, the AC/DC characteristics of the optimized dual field plate (SG-FP) are demonstrated. We observed that the source–gate dual field plate (SG-FP) device shows a 6.70% and 4.09% improvement in breakdown voltage compared to individual source field plate (S-FP) and gate field plate (G-FP) designs, respectively. This work shows that the proposed dual field plate device is used in power switching, high-power, and RF/Microwave applications due to its superior breakdown voltage performance, reduction in parasitic capacitances, and optimal cut-off frequency.

Normally-Off Metal-Insulator-Semiconductor P-GaN gated AlGaN/GaN high electron mobility transistors with low gate leakage current

In this study, a normally-off AlGaN/GaN metal–insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with p-GaN layer were processed, which possess a high threshold voltage and a low gate leakage current due to metal–insulator-semiconductor (MIS) gate structure. A SiNx layer as the insulator layer was deposited between p-GaN layer and gate electrode. The dependent of device performance on SiNx thickness was investigated. Moreover, the threshold voltage of normally-off MIS-HEMT was emphatically discussed with different insulator layer thickness. It demonstrates that obviously positive shifting for threshold voltage from 1.5 to 6 V was achieved by increasing the SiNx thickness from 0 to 20 nm, while the channel mobility was comparable for all samples. Besides, the introduction of MIS gate structure is also beneficial for suppressing the gate leakage current and improving the maximum gate voltage swing owing to the high breakdown field of approximately 8.3 MV/cm.

Spray Pyrolyzed Amorphous InGaZnO for High Performance, Self‐Aligned Coplanar Thin‐Film Transistor Backplanes

AbstractHigh‐performance, spray‐pyrolyzed amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin‐film transistor (TFT) with self‐aligned (SA) coplanar structure is demonstrated. The spray‐pyrolyzed a‐IGZO film exhibits bubbles‐free smooth surface roughness (0.81 nm) and low oxygen‐related defects (22.5%). The fluorine‐doped a‐IGZO film shows a low resistivity of 1.18 × 10−3 Ω‐cm by NF3 plasma treatment. This is sufficient to obtain ohmic contact with the source/drain electrodes and doped IGZO in the offset region of the SA coplanar TFT. The spray‐pyrolyzed a‐IGZO TFT exhibits the field‐effect mobility (µFE) of 18.17 cm2 V−1 s−1, the threshold voltage (VTH) of −1.52 V, the subthreshold swing (SS) of 0.266 V dec−1, and a high on/off current ratio (Ion/Ioff) over 108 with a very low gate leakage current (<10−13 A). The hysteresis‐free and highly stable performances are achieved due to the excellent a‐IGZO channel and SiO2 gate insulator interface. A twenty‐three‐stage ring oscillator is demonstrated with SA coplanar TFTs, exhibiting a high oscillation frequency of 2.66 MHz and a low propagation delay of 8.17 ns/stage. Therefore, the spray‐pyrolyzed a‐IGZO film can be a promising metal oxide semiconductor for high‐performance TFTs backplane in large areas and high‐resolution display applications.

Low Leakage Current and High Breakdown Field AlGaN/GaN MIS-HEMTs Using PECVD-SiNx as a Gate Dielectric.

In this paper, SiNx film deposited by plasma-enhanced chemical vapor deposition was employed as a gate dielectric of AlGaN/GaN high electron mobility transistors (HEMTs). We found that the NH3 flow during the deposition of SiNx can significantly affect the performances of metal–insulator–semiconductor (MIS) HEMTs. Compared to that without using NH3 flow, the device with the optimized NH3 flow exhibited three orders of magnitude lower gate leakage current, two orders of magnitude higher ON/OF drain current ratio, and an increased breakdown field by 69%. In addition, an in situ N2 plasma surface treatment prepared prior to SiNx deposition can further improve DC performances of MIS-HEMTs to a very low gate leakage current of 10−9 mA/mm and a high ON/OFF drain current ratio up to 109 by reducing the interface state density. These results demonstrate the great potential for using PECVD-SiNx as a gate dielectric in GaN-based MIS-HEMTs.

(Invited) Rare Earth Oxides on Wide Band Gap Semiconductors

Globally, most recent power electronics converter and device technology has been driven by the unprecedented demand seen within the automotive sector [1]. The latter demands power converters with near 100% energy efficiency, lightweight, compact and reliable. Wide band gap (WBG) semiconductor materials such as GaN and 4H-SiC have emerged as contenders to replace Si in many power electronics applications. Currently, GaN devices based on the high electron mobility transistor (HEMT) architecture are limited commercially to a maximum of 650 V [2,3]. GaN HEMTs have traditionally suffered from a poor thermal conductivity and the “current collapse” phenomenon, limiting their ability to operate within harsh environments. On the other hand, 4H-SiC has a few reliability issues that limit its ubiquitous application in the automotive sector [2]. Currently the GaN based Metal-Insulator-Semiconductor (MIS)-HEMT device is seen to demonstrate superior performance in power electronics applications over the Schottky gate counterpart, due to its inherently lower gate leakage current, together with the ability to provide larger forward gate voltage swing by engineering the threshold voltage between depletion and enhancement mode operation and also an improved gate-drain breakdown voltage. High band gap gate dielectric materials are preferable as they can provide higher tunnelling barriers for electrons and holes, which result in lower gate leakage current. Furthermore, high dielectric constant (high-k) material is also necessary for improved electrostatic control over the channel and improved on-current, which in-turn results in higher transconductance. In terms of SiC based devices, the use of SiO2 proves to be a bottleneck in exploiting full potential of SiC due to the low value of dielectric constant of SiO2 [4]. Since the oxide is subjected to an electric field that is ~2.5x the field in the semiconductor, the breakdown of SiO2 occurs first, and hence causes the breakdown of SiO2/4H-SiC based devices well below the critical electric field of SiC. This shortcoming led to the exploration of high-k dielectrics as gate stacks in 4H-SiC MIS based devices as well as for surface passivation. It is worth noting that SiO2 is the only dielectric commercially used for SiC devices largely due to the unavailability of a reliable high-k dielectric alternative. Most published results focus on use of Al2O3 and HfO2 films [5], however they have yet to become used mainstream in 4H-SiC devices.In this paper, two rare earth high-k oxides, Y2O3 and Sc2O3, both with dielectric constant >10, have been studied in terms of their suitability as gate dielectrics on GaN and 4H-SiC. The oxide films were prepared by radio frequency (RF) magnetron sputtering (Sc2O3) and ion gun sputtering (Y2O3). The substrates were cleaned with Kr ions with anode current of ~ 50 mA and accelerating voltage of 3 kV for 1-2 hours. Then metallic Y was sputtered using pressure of 1.5 x 10-5 mbar and current of 26 mA, which was followed by exposure to O2 to form Y2O3 films. Sc2O3 films were deposited using Moorfields nano-PVD (physical vapour deposition) equipment with circular Sc2O3 target of 99.99% purity using RF power of 60 W and a gas flow of 0.5 sccm for 3 nm film and 3 sccm for 40 nm film. The films were also deposited simultaneously on Si to be used as reference samples for variable angle spectroscopic ellipsometry (VASE) measurements to ascertain their thickness and optical properties. The X-ray photoelectron spectroscopy (XPS) was used to characterise comprehensively the oxide/semiconductor interface. The capacitance voltage measurements on MIS stacks were used to determine permittivity of deposited oxides. The complete band alignment of oxide/WBG semiconductor as well as comprehensive comparison to state of the art data will be presented and discussed in full paper. Acknowledgement. The UKIERI IND/CONT/G/17-18/18 and F.No.184-1/2018(IC) project funded by the British Council; UKRI GCRF GIAA award 2018/19 and EP/P510981/1, funded by the EPSRC, UK. References. [1] http://www.yole.fr/Compound_Semiconductor_Monitor_Q1.aspx. [2] Li et al., Materials 14, 5831 (2021); [3] Gonzalez et al. IEEE Trans. Ind. Electron. 67, 7375 (2020); [4] A. Siddiqui et al., J. Mater. Chem. C 9, 5055 (2021); [5] Bencherif et al., Appl. Phys. A 126, 854 (2020).

Positive Shifting of Vth with Enhanced DC Performance in AlGaN/GaN Schottky-Gate HEMT through Optimized UV/O3 Treated Gate Interface and Thermal Engineering

The surface condition under the gate is critically important to improve the device characteristics and thus reliability of the AlGaN/GaN high electron mobility transistor (HEMT). In this report, we demonstrated the reduction of leakage current (IG) with betterment of current collapse in Al0.25Ga0.75N/GaN Schottky gate (SG)-HEMT by improving metal/GaN interface using optimized ultraviolet-ozone (UV/O3) plasma treatment with post metal annealing modulation at 450 °C. The x-ray photoelectron spectroscopy (XPS) was used to verify the formation of GaOXNY layer at the metal/GaN interface. Owing to, the screening of the internal/external polarization charges by 10 min. UV/O3 surface plasma treatment and incremental increase of Schottky barrier height (Φ B) with post metal annealing modulation, resulted in the positive shifting of threshold voltage (VTH) in SG-HEMT. Due to the combined effects of the UV/O3 plasma treatment and metal annealing modulation, the magnitude of the interface trap density were effectively reduced to one order of magnitude, which further improved the current collapse significantly in SG-HEMT to 2.5% from 12.2%. The 10 min. UV/O3 treated SG-HEMT with PMA modulation exhibited decent performance with an IDMAX of 620 mA mm−1, a GMMAX of 135 mS mm−1, a threshold voltage (VTH) of −1.8 V, a higher ION/IOFF ratio of approximately a subthreshold swing (SS) of 83 mV dec−1, with a low gate leakage current of

Improved Ion/Ioff Current Ratio and Dynamic Resistance of a p-GaN High-Electron-Mobility Transistor Using an Al0.5GaN Etch-Stop Layer.

In this study, we investigated enhance mode (E-mode) p-GaN/AlGaN/GaN high-electron-mobility transistors (HEMTs) with an Al0.5GaN etch-stop layer. Compared with an AlN etch-stop layer, the Al0.5GaN etch-stop layer not only reduced lattice defects but engendered improved DC performance in the device; this can be attributed to the lattice match between the layer and substrate. The results revealed that the Al0.5GaN etch-stop layer could reduce dislocation by 37.5% and improve device characteristics. Compared with the device with the AlN etch-stop layer, the p-GaN HEMT with the Al0.5GaN etch-stop layer achieved a higher drain current on/off ratio (2.47 × 107), a lower gate leakage current (1.55 × 10−5 A/mm), and a lower on-state resistance (21.65 Ω·mm); moreover, its dynamic RON value was reduced to 1.69 (from 2.26).

High‐Performance GaN HEMTs with ION/IOFF ≈1010 and Gate Leakage Current <10−11 A mm−1 Using Ta2O5 Dielectric

Herein, Ta2O5 high‐k gate dielectric‐based GaN high electron‐mobility transistors (HEMTs) with a high I ON/I OFF ratio and low gate leakage current are demonstrated without any significant deterioration of the other performance parameters. Ta2O5 with an average surface roughness of 1.8 nm and a dielectric constant of ≈26 are grown by sputtering and annealing in O2. The bandgap, valence, and conduction band offsets with Al0.3Ga0.7 N are 4.85, 0.24, and 0.61 eV, respectively. The reverse gate leakage current at −7 V is observed to be 1.2 ×10−10 A mm−1 for 5 nm and <1.0×10−11 A mm−1 for 20 and 30 nm oxide thickness compared to 5.0 × 10−6 A mm−1 for the control sample. This current is among the lowest ever reported for GaN‐based oxide‐HEMTs without significantly sacrificing other performances. The I ON/I OFF ratio is 2 × 109, 7 × 109, and 1 10 for 5, 20, and 30 nm oxide thickness, respectively, as compared to 2 × 108 for the control sample. The interface–state–density is estimated to be 1.5 × 1013 cm−2 eV−1. I DS,sat is measured to be 710, 700, and 690 mA mm−1 for 5, 20, and 30 nm Ta2O5 thickness, respectively, compared to 725 mA mm−1 for the control sample. The presence of oxide does not change the other characteristics much.

Low Leakage and High ION/IOFF Ratio in Partial Gated AlGaN/GaN Nanowire Field‐Effect Transistors

Lateral nanowire (NW) field‐effect transistors are fabricated by a top‐down approach on an AlGaN/GaN heterostructure. A combination of dry and anisotropic wet etching is used to form the NW. The channel is controlled by a 2D electric field originating from two partial gates on the parallel sides of the nanowire channel. While a larger overlap of the gate with the channel region, as in a gate‐all‐around transistor, improves gate control in terms of transconductance gm, gate leakage current and ION/IOFF deteriorate. Partial overlapping gate transistors are found to provide a trade‐off, providing extremely low gate leakage current (≈10 μA cm−2), very low IOFF (100 fA μm−1), and very high ION/IOFF (5 × 108). Despite the nature of the partial gate, a good subthreshold swing (SS) of ≈79 mV decade−1 is observed. Various transistor performance parameters can be tuned within a certain window of trade‐offs between them as the transistor evolves from a partial gate to a gate‐all‐around structure. A 1D nature of the channel near the transistor threshold voltage is found to offset the limitations of the partial gate.

High Voltage and Low Leakage GaN-on-SiC MISHEMTs on a “Buffer-Free” Heterostructure

The performance of a novel ‘buffer-free’ AlGaN/GaN-on-SiC MISHEMTs for power switching applications is demonstrated in this letter. High voltage operation with exceptionally low gate and drain leakage currents is shown. A specific on-resistance of 3.61 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Omega } \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and an abrupt breakdown voltage of 1622 V at a drain current of 22 nA/mm is achieved. Using two-terminal breakdown measurements, nitrogen-implanted GaN display breakdown fields of 0.96 MV/cm. The semi-insulating SiC substrate is capable of suppressing vertical leakage currents, ensuring that off-state operation is limited by lateral breakdown. The impact of electron trapping effects on dynamic on-resistance is small up to a drain quiescent voltage of at least 240 V. Drain current transient characteristics display a 14% increase in dynamic on-resistance with respect to quiescent drain bias, and a negligible change in resistance up to 100 ms. These types of ‘buffer-free’ heterostructures are of interest for power electronic applications above 1000 V and with potential for co-integration of power and RF-electronics.