Low Gate Count Research Articles

A variation resilient keeper design for high performance domino logic applications

High performance is one of the essential features of the electronic devices, which are needed to cope with the consumer demand of high frequency operation thus leading to a complex design. As dynamic CMOS corresponds to high speed operation, a low gate count and power/noise efficient configuration of domino logic circuit is tendered in this article. The simulation is executed for 90 nm CMOS process node at a power supply of 1V to formulate the design of AND, OR and XOR operation. The post-layout study of 2 input OR gate records an average power dissipation and delay of 17.40 μW and 86.88 ps, which are noted to measure a variability of 5.76% and 4.30% respectively when investigated under 5000 statistical runs of Monte-Carlo. The stability of the design is observed as power, delay and PDP are noted to sustain a shift of as tiny as 24.84 nW, 271 fs and 2.68 aJ respectively following a 1 °C variation in temperature. The configuration is also tested for wide fan-in gates and found to carry resilience under extreme deviations of process–voltage–temperature. The scalability of proposed domino setup is validated at a lower process node of UMC 28 nm.

Sboxgates: A program for finding low gate count implementations of S-boxes

sboxgates: A program for finding low gate count implementations of S-boxes

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

SummaryConventional complementary metal oxide semiconductor (CMOS)‐based dedicated true random number generator (TRNG) and physically unclonable function (PUF) designs have exhibited higher energy consumption and large area overhead with technology scaling. In contrast, this paper for the first time presents emerging tunnel field‐effect transistor (TFET)‐based ultra‐lightweight reconfigurable TRNG and PUF design. A unique methodology is proposed that considers p‐i‐n forward current characteristics to generate random keys for PUF and TRNG designs. Leveraging the p‐i‐n forward current of TFET, a ring oscillator (RO) is designed that exhibits variation in the operating frequency and acts as the main source of entropy for both PUF and TRNG. The TRNG in the proposed design is robust and passed all the National Institute of Standards and Technology (NIST) tests. Considering the variation in p‐i‐n forward current, the uniqueness of PUF is calculated as 47.5% and 46% at a supply voltage of 0.5 and 0.45 V, respectively. Moreover, PUF achieves high reliability of 82% and 88.7% with supply voltage and temperature variations, respectively. The proposed design is proved to be compact with relatively lower gate count and shows low energy consumption of 4.8 pJ/bit at 0.5‐V supply voltage. With these performance metrics, the proposed design is highly suitable for resource‐constrained internet of things (IoT).

A Low gate count reconfigurable architecture for biomedical signal processing applications

A new reconfigurable architecture for biomedical applications is presented in this paper. The architecture targets frequently encountered functions in biomedical signal processing algorithms thereby replacing multiple dedicated accelerators and reports low gate count. An optimized implementation is achieved by mapping methodologies to functions and limiting the required memory leading directly to an overall minimization of gate count. The proposed architecture has a simple configuration scheme with special provision for handling feedback. The effectiveness of the architecture is demonstrated on an FPGA to show implementation schemes for multiple DSP functions. The architecture has gate count of approx25k and an operating frequency of 46.9 MHz.

A power efficient PFD-CP architecture for high speed clock and data recovery application

This paper explores a speed and power improved dead zone free, low gate count CMOS phase frequency detector with charge pump (PFD-CP) for clock and data recovery application. Implemented in 90 nm CMOS technology, the proposed circuit configuration estimates a layout area of 420.66 μm2 and burns a low power as small as 172.10 μW when simulated with 5 GHz frequency at a power supply of 1.2 V at Cadence Virtuoso platform. With the elimination of reset path available in conventional PFD, this architecture doesn’t only become blind zone free, but it also offers a lower phase noise and output noise of − 142.46 dBc/Hz and − 131.145 dBc/Hz respectively at 1 MHz offset. We have also studied the performance metrics with skew and without skew at different extreme corners for schematic and post layout to manifest the variation awareness and robustness of the circuit. The scalability of the circuit arrangement is also endorsed at lower CMOS technology.

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware

Digital signal processing (DSP) kernel-based intellectual property (IP) core forms an integral ingredient of consumer electronics devices. Thus, protection of these IP cores against reverse engineering attack is crucial. Functional obfuscation serves as a powerful mechanism to counter this hardware threat. However, functional obfuscation methodologies for DSP cores use security logics that are not lightweight and are prone to removal attack by an adversary. This paper presents a novel security mechanism for protecting functionally obfuscated DSP core against removal attack using low-cost, low-power key encryption hardware. The proposed methodology using lightweight secure hashing algorithm (SHA-512)-based key encryption custom hardware reconfigures the key-bits (resulting into structural reconfiguration) of the locking logic in a functionally obfuscated DSP design augmented with the complete logic synthesis of the design. This hinders the detection of the locking logic in the obfuscated design due to camouflaging. The proposed mechanism integrated with the functional obfuscation framework yielded lower power, lower gate count, and enhanced security compared with an existing approach. An average reduction of 25.86 % in gate count and power as well as the average enhancement of 43.75 % in security against removal attack was obtained in the proposed approach compared with a recent existing approach.

An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data

The high speed wireline communication suffers from a lot of signal quality issues such as jitter and swing, which eventually leads to higher probability of data loss. As the current mode multiplexer, being the integral cell of any transceiver circuit guides to Serialize data in high rate, its arrangement is of utmost importance. This work explores a novel configuration of multiplexer embedded with cross-coupled NMOS latch after integrating the Transmission Gate (TG) principle with the MOS Current Mode Logic (MCML). The proposed configuration reads an average power, delay and power-delay product (PDP) of as tiny as 135.7 μW, 20.16 ps and 2.736 fJ, respectively when simulated for 90 nm CMOS using Cadence Virtuoso at 10 GHz switching frequency and 1 V power supply. The process variation is performed at different corners through Monte-Carlo runs with ‘no skew’ and ‘5% process skew’ variation at both pre-layout and post-layout to prove the robustness of the proposed Mux-Latch, which is employed to tender a new low gate count and energy efficient variation aware Serializer circuit capable of offering a data rate of as high as 50 Gbit/s. The entire circuit is also validated at lower technology nodes like 28 nm UMC.

Local Binary Pattern Circuit Generator With Adjustable Parameters for Feature Extraction

In the field of computer vision, local binary pattern (LBP) is one of the most popular feature extraction method and has been used in many object detection frameworks. To efficiently extract LBP features in high-resolution images, hardware architecture is needed to disperse CPU burden and to improve the entire object detection performance. In this paper, a hardware implementation of an approximated LBP method with adjustable parameters is introduced. For simulation, Taiwan Semiconductor Manufacturing Company <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> technology is used to implement the LBP hardware, and the hardware can achieve 500 MHz with lower gate count than previous study. The proposed LBP circuit is applied to the pedestrian classification application and the evaluation results show that the approximated LBP values generated by our circuit can achieve comparable classification accuracy with the primitive LBP method. Additionally, the proposed LBP hardware provides adjustable parameters to fit different applications while requires fewer hardware costs as compared with the existing work.

A tree search algorithm for low multiplicative complexity logic design

Low multiplicative complexity logic design is a useful heuristic to achieve low gate count implementation of logic circuit. In this work, we propose a deterministic approach based on the currently known lower and upper bounds of multiplicative complexity for logic minimization problems with not more than five inputs. The proposed tree search algorithm achieves circuit minimization through decomposition of Positive Polarity Reed–Muller expressions. This approach allows low multiplicative complexity logic design to be executed without the consistency issue associated with the randomized approach in the original algorithm. Experimental results show over 85% improvement in computation time compared to solving the same problems using the previous randomized approach. We also demonstrate that the quality of results produce by the proposed algorithm is comparable, and in some cases, better than the results reported in previous works using the same heuristic.

Review and Comparative Analysis of Stream Cipher for LTE Technology

With the advancement in the telecommunication system, fast evolution in mobile communication has been observed. Besides this there are many applications in the wireless sensor network which needs limited resources such as low gate count, low power consumption, low memory etc. These applications are mobile phones, smart grids, electronic identity cards, and RFID (Radio Frequency Identification Devices) tags. In this paper, we have discussed about the evolution of communication technology from first generation to fourth generation. We have also studied the security issues of LTE (long Term Evolution) technology. We have surveyed the various stream ciphers and comparative analysis of the various stream ciphers has also been done. On the basis of comparative analysis we have provided the research direction for the future work.

Finding Near-Optimum Message Scheduling Settings for SHA-256 Variants Using Genetic Algorithms

One-way hash functions play an important role in modern cryptography. Matusiewicz et al. proved that the message scheduling is essential for the security of SHA- 256 by showing that it is possible to find collisions with complexity 264 hash operations for a variant without it. In this article, we first proposed the conjecture that message scheduling of SHA algorithm has higher security complexity (or fitness value in Genetic algorithm) if each message word (Wt) involves more message blocks (Mi) in each round. We found some evidence supports the conjecture. Consider the security of SHA-0 and SHA-1. Since Chabaud and Joux shown that SHA-1 is more secure than SHA-0. Further, Wang found collisions in full SHA-0 and SHA-1 hash operations with complexities less than 239 and 269, respectively. We found it is consistent from the viewpoint of message blocks (terms) involved in each message word. It clearly shown that the number of terms involved in SHA-1 is more than that in SHA-0, taking W27 as an example, 14 and 6, respectively. Based on the conjecture we proposed a new view of complexity for SHA- 256-XOR functions, a variant of SHA-256, by counting the terms involved in each equation, instead of analyzing the probability of finding collisions within SHA-256-XOR hash function. Our experiments shown that the parameter set in each equation of message schedule is crucial to security fitness. We applied genetic algorithms to find the near-optimal message schedule parameter sets that enhance the complexity 4 times for SHA-1 and 1.5 times for SHA-256-XOR, respectively, when compared to original SHA- 1 and SHA-256-XOR functions. The analysis would be interesting for designers on the security of modular-addition-free hash function which is good for hardware implementation with lower gate count. And the found message schedule parameter sets would be a good reference for further improvement of SHA functions.

FPGA Implementation of an LFSR based Pseudorandom Pattern Generator for MEMS Testing

strides in programmable logic density, speed and hardware description language (HDL) have empowered the engineer with the ability to implement high-performance digital functionality within field programmable gate array (FPGA). Linear feedback shift resister (LFSR) has become one of the central elements used in testing and self testing of contemporary complex electronic systems like processors, controllers and integrated circuits (ICs). This paper presents the FPGA implementation of an LFSR based pseudorandom pattern generator. This LFSR has the characteristics of high speed, low power consumption and it is especially suited in processing environment where uniform distribution random numbers are required. A typical application of the pattern generator considered in this work is the testing of micro- electro-mechanical-system (MEMS), where low power consumption is required. Very high speed integrated circuit HDL (VHDL) was used to implement the LFSR on FPGA. A testbench in VHDL was used to verify the correctness of the design. The compiled VHDL code was been synthesized into gate level. Area and timing optimization were done to achieve a very low gate count of 436 and increase the design speed to 178MHz Mentor Graphics and Xilinx ISE 6, electronic design automation (EDA) tool suite and DIGILENT D2SB PROTO BOARD were used for the overall FPGA implementation process.

A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link

This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively.

A new FIFO for transferring data between two unrelated clock domains

A new simple-to-design FIFO that allows data transfer between two clock domains of unrelated frequencies has been developed. The fully synchronous interfaces significantly ease the system-on-chip integration process. With a relatively low gate count, the proposed FIFO allows the producer and consumer to put/get data at their respective frequencies (1 datum/clock cycle) till it gets filled, then the rates converge to the lower of the two frequencies. The maximum initial latency is three cycles of the consumer's clock. Several manifestations of the FIFO have been developed for different design cases including producer/consumer data width mismatch. Operation of the FIFO has been verified using both gate-level simulations and SPICE simulations with a 0.13 µm, 1.2 V technology. An 8-cell FIFO showed proper operation at producer and consumer clock frequencies of 2 and 3.125 GHz, respectively, with a data transfer rate of more than 2 giga datum/s and an average power of 721 µW.

Electronic Resource Expenditure and the Decline in Reference Transaction Statistics in Academic Libraries

The current study investigates factors influencing increase in reference transactions in a typical week in academic libraries across the United States of America. Employing multiple regression analysis and general linear modeling, variables of interest from the Academic Library Survey (ALS) 2006 survey (sample size 3960 academic libraries) were analyzed. Findings indicated that spending more on electronic resource in academic libraries leads to an increase rather than a decrease in numbers of reference transactions in a typical week recorded. Additionally, the effect of having low, medium or high gate counts is different for high, medium and low spenders on electronic resources within academic library groups surveyed on the outcome variable.

FAST ALGORITHM ANALYSIS AND BIT-SERIAL ARCHITECTURE DESIGN FOR SUB-PIXEL MOTION ESTIMATION IN H.264

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.

A Bit-Serial Multiplier Architecture for Finite Fields Over Galois Fields

Problem statement: A fundamental building block for digital communication is the Public-key cryptography systems. Public-Key Cryptography (PKC) systems can be used to provide secure communications over insecure channels without exchanging a secret key. Implementing Public-Key cryptography systems is a challenge for most application platforms when several factors have to be considered in selecting the implementation platform. Approach: The most popular public-key cryptography systems nowadays are RSA and Elliptic Curve Cryptography (ECC). ECC was considered much more suitable than other public-key algorithms. It used lower power consumption, has higher performance and can be implemented on small areas that can be achieved by using ECC. There is no sub exponential-time algorithm in solving the Elliptic curve discrete logarithm problem. Therefore, it offers smaller key size with equivalent security level compared with the other public key cryptosystems. Finite fields (or Galois fields) is considered as an important mathematical theory. Results: Thus, it plays an important role in cryptography. As a result of their carry free arithmetic property, they are suitable to be used in hardware implementation in ECC. In cryptography the most common finite field used is binary field GF (2m). Conclusion: Our design performs all basic binary polynomial operations in Galois Field (GF) using a microcode structure. It uses a bit-serial and pipeline structure for implementing GF operations. Due to its bit-serial architecture, it has a low gate count and a reduced number of I/O pins.

Monitoring embedded software timing properties with an SoC-resident monitor

Many safety–critical software applications are hard real-time systems. They have stringent timing requirements that have to be adhered to. Functional timing requirements need to interact properly with performance timing requirements. A novel runtime monitor that can check for proper timing behaviour of software, in the actual implementation environment, is presented. The monitor can be synthesised from the software&apos;s timing requirements specification and instantiated in the programmable digital logic of a system on chip (SoC)-based device. Since the monitor is synthesised from the program&apos;s requirements, new monitors can be automatically generated for new programs. Since the SoC-based monitor is deeply embedded, it can operate at the full processor speed and will have access to the internal registers of the processing system. A low gate count, non-invasive monitor is achievable. A case study example, based on a design for an electronic automotive gear controller system, is presented. The study shows that the monitor is capable of detecting program timing violations, in the implementation environment, even though the software design had been properly verified against stated requirements. The monitor scheme can be used as a supplementary test solution or the monitor can be built into a product for lifetime monitoring of timing behaviour, so as to enhance the product&apos;s reliability.

An Efficient FFT Processor for DAB Receiver Using Circuit-Sharing Pipeline Design

With the upcoming fourth generation wireless systems and convergence of multiple radio standards into a single terminal, building blocks are needed that can be configured for computing various algorithms used in different standards. Given these trends and requirements, in our previous paper we successfully proposed a circuit-sharing design for the DAB receiver to integrate the FFT (fast Fourier transform) and IMDCT (inverse modified discrete cosine transform) operations into the same functional circuit. The proposed technique reduces hardware overhead, enhances circuit efficiency and significantly reduces the cost of DAB receivers. To further improve the efficiency of our previous work, this investigation proposes another alternative design named the circuit-sharing pipeline design (CSPD) using a single processor with a pipeline scheme to combine two functions, FFT and IMDCT, into the same circuit. The proposed method reduces the required chip area and cost of DAB receivers. Analyzing the existing relationship among IMDCT, DCT (discrete cosine transform) and FFT, the IMDCT function can be replaced using a FFT function. Therefore, it is not necessary to design an extra circuit for IMDCT. The arithmetic unit in the FFT processor can be significantly reduced due to employing the pipeline scheme. Consequently, the circuit redundancies in the IMDCT and FFT functions can be easily eliminated to allow exploitation of the decreased chip area. Results of this study demonstrate that the proposed design can provide advantages such as low gate count and small memory size in the DAB (digital audio broadcasting) receiver.

High-performance phased binary coding

A novel, parallel and compact design for phased binary coding is described. Such an algorithm is widely used in dictionary-based lossless data compression and permits more efficient coding of dictionary references during dictionary growth. Parallelism within the algorithm is exploited to reduce the critical path while still maintaining a low gate count.