A variation resilient keeper design for high performance domino logic applications

Abstract

High performance is one of the essential features of the electronic devices, which are needed to cope with the consumer demand of high frequency operation thus leading to a complex design. As dynamic CMOS corresponds to high speed operation, a low gate count and power/noise efficient configuration of domino logic circuit is tendered in this article. The simulation is executed for 90 nm CMOS process node at a power supply of 1V to formulate the design of AND, OR and XOR operation. The post-layout study of 2 input OR gate records an average power dissipation and delay of 17.40 μW and 86.88 ps, which are noted to measure a variability of 5.76% and 4.30% respectively when investigated under 5000 statistical runs of Monte-Carlo. The stability of the design is observed as power, delay and PDP are noted to sustain a shift of as tiny as 24.84 nW, 271 fs and 2.68 aJ respectively following a 1 °C variation in temperature. The configuration is also tested for wide fan-in gates and found to carry resilience under extreme deviations of process–voltage–temperature. The scalability of proposed domino setup is validated at a lower process node of UMC 28 nm.