A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design

Abstract

With continued scaling of VLSI circuits, reliability has emerged out as one of the major circuit design challenges. Systematic die-to-die, random on-die as well as temperature and supply voltage variations are major sources of performance degradation which leads to unreliable circuits. Further, with reduced short channel effects at highly scaled nodes, the FinFET has recently been emerged as a suitable replacement of CMOS in the VLSI industry. Wide fan-in FinFET domino logic OR gate is one such circuit, which serves as an integral part of register file in a high-speed FinFET microprocessor. This circuit inherently suffers from low noise immunity which get worsens with circuit parameter variations due to process and temperature variations. At highly scaled technology nodes, it has been studied that the effects of on-die random process variation surpass the effects of systematic variations. Furthermore, at deep sub-nanometer scale the effect of process variation on device parameters is higher in FinFET as compared to CMOS. In this research work a reliable current mirror-based wide fan-in FinFET domino OR gate is proposed for temperature, random on-die and systematic die-to-die process variation tolerance. Simulation results at 32 nm FinFET process show that the proposed design is capable of maintaining high noise immunity (Unity Noise Gain of nearly 0.4 V) at all process corners and a constant performance (with reduced delay by 30% as compared to conventional design) in the presence of systematic as well as random process and temperature variations.