Low Gate Count Research Articles

A cost-effective 8×8 2-D IDCT core processor with folded architecture

A dedicated cost-effective core processor of the 8/spl times/8 two-dimensional (2-D) inverse discrete transform (IDCT) architecture based on the direct realization approach is proposed. The folding scheme is developed to obtain a low gate-count and high throughput. The experimental result shows that the chip's throughput is one pixel per clock cycle with a structure of 78 K transistors, which reveals that the low cost of VLSI implementation is more attractive than most of previously reported chips. With 0.6 /spl mu/m CMOS, double metal technology, the chip is a standard-cell implementation and requires a core size of 4.4/spl times/2.8 mm/sup 2/, and is able to operate at a clock rate of more than 100 MHz.

A new architecture for a parallel finite field multiplier with low complexity based on composite fields

A bit parallel structure for a multiplier with low complexity in Galois fields is introduced. The multiplier operates over composite fields GF((2/sup n/)/sup m/), with k=nm. The Karatsuba-Ofman algorithm (A. Karatsuba and Y. Ofmanis, 1963) is investigated and applied to the multiplication of polynomials over GF(2/sup n/). It is shown that this operation has a complexity of order O(k/sup log23/) under certain constraints regarding k. A complete set of primitive field polynomials for composite fields is provided which perform module reduction with low complexity. As a result, multipliers for fields GF(2/sup k/) up to k=32 with low gate counts and low delays are listed. The architectures are highly modular and thus well suited for VLSI implementation.

Efficient filter design for IS-95 CDMA systems

An efficient filter design method for the design of a relatively complex low pass filter specified in the IS-95 code division multiple access (CDMA) standard is presented The described circuit details and algorithm have been tested by means of computer simulation and hardware experimental result. Using field programmable gate array (FPGA) technology, a low power and gate count finite impulse response (FIR) filter design for the transmitter is realized. For the receiver, canonical digit representation of signed numbers are used to reduce the complexities in multiply operations. The critical spectral degradation due to quantization error of the sample and due to truncation of coefficient accuracy is simulated. Practical design guidelines are provided. The described design details demystify the challenging concept and difficulty in an IS-95 standardized filter. In addition, through the use of the implemented filter hardware for the modulator, spectral regrowth in nonlinear amplified IS-95 CDMA is demonstrated and is shown to correlate very closely with computer simulation. This work leads to a cross-correlative technique that will improve spectral regrowth for CDMA systems. Similar methods are being employed in Feher's (1995) family of PSK modulation schemes, a technique which yields lower spectral regrowth in nonlinearly amplified channels.

MPEG decoder architecture for embedded applications

A determinate global data transfer timing scheme will significantly reduce the complexity of global control and ease constraints on sub-modules. Such a scheme allows to construct functional modules based on an explicit performance and data flow requirement. A very low gate count hardware architecture for MPEG decoder is presented to demonstrate the concept.

HLL enhancement for stack based processors

Stack machines, or stack based processors, have long been pigeon-holed as FORTH processors; specialised devices with little relevance for high level language applications. The failure of stack machines to address the issue of high level language support, and C in particular, has prevented wider acceptance of this promising technology despite the potential benefits of simpler hardware and low gate counts. Our research has centred upon eliminating cache and memory dependence, reducing the limits imposed by external bandwidths ◊ ◊ This research is sponsored by Microprocessor Engineering Ltd (Southampton U.K.). . Having previously introduced a compact multiple-instruction-per-word stack-based encoding strategy in [Bailey93a], we now present a revised model, assessing its performance with compiled C benchmarks The compiler was developed by Damien Kelly, University of Teesside. , and stressing minimisation of memory dependence.

Implementation of the arbitrary free-space optical interconnections with equal path lengths by use of a layered structure

We describe and demonstrate a scheme to implement arbitrary space-variant optical interconnections with equal path lengths in free-space, using a layered structure for a low gate count and high throughput. We discuss extending the technique to reduce the number of layers by performing small group interconnections on laterally separable locations.

A parallel monotonic classification machine

Current parallel machines, such as array processors and Prolog or Lisp machines, are not optimized to execute monotonic classification tasks. A new special-purpose parallel computer is proposed, which efficiently solves this important type of problem from examples it encounters. After the study of sufficient examples, the macine is capable of classifying objects which it might have never seen before. What makes the machine unique is its low gate count when compared with its counterparts.

A systolic, linear-array multiplier for a class of right-shift algorithms

A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only upper bound [n]/2 cells are needed for a full n by n multiply. A module-multiplier is then developed by incorporating a Montgomery type of module-reduction. Two such multipliers interconnect to form a purely systolic module exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus. >

A flexible approach to emitter-coupled logic arrays

The ECCSL arrays have been successfully fabricated using two levels of metalization on 120 by 120-mil chips. The yield, fabrication, and performance studies of these arrays, while not yet complete, indicate that current mode logic arrays of 10 to 30 gates are entirely feasible. This is especially true if the size of the chips are reduced as much as possible (preferably below 0.10 by 0.10 inch.) Indications are that arrays with relatively low gate counts (10 to 30 gates) greatly reduce the testing problems usually associated with array technology.