A new FIFO for transferring data between two unrelated clock domains

Abstract

A new simple-to-design FIFO that allows data transfer between two clock domains of unrelated frequencies has been developed. The fully synchronous interfaces significantly ease the system-on-chip integration process. With a relatively low gate count, the proposed FIFO allows the producer and consumer to put/get data at their respective frequencies (1 datum/clock cycle) till it gets filled, then the rates converge to the lower of the two frequencies. The maximum initial latency is three cycles of the consumer's clock. Several manifestations of the FIFO have been developed for different design cases including producer/consumer data width mismatch. Operation of the FIFO has been verified using both gate-level simulations and SPICE simulations with a 0.13 µm, 1.2 V technology. An 8-cell FIFO showed proper operation at producer and consumer clock frequencies of 2 and 3.125 GHz, respectively, with a data transfer rate of more than 2 giga datum/s and an average power of 721 µW.