Low-frequency Noise Behavior Research Articles

Effects of series resistance and interface properties on the operation of AlGaN/GaN high electron mobility transistors

The AlGaN/GaN high electron mobility transistor (HEMT) is considered a promising device for high-power, high-frequency, and high-temperature applications, as well as high-sensitivity sensors. However, several issues related to mobility, interface properties, and series resistance need to be clarified for a better understanding of the physical operation of AlGaN/GaN HEMTs and for further optimization of their performance. In this work, the electrical properties of AlGaN/GaN HEMTs, including the effects of series resistance, and interface properties with mobility degradation factors were investigated in detail. In addition, the low-frequency noise behavior of AlGaN/GaN HEMTs was examined with a carrier number fluctuation model that considered series resistance effects.

Junctionless Versus Inversion-Mode Gate-All-Around Nanowire Transistors From a Low-Frequency Noise Perspective

The low-frequency noise behavior of junctionless (JL) gate-all-around (GAA) nanowire (NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It is shown that the predominant 1/f-like noise is governed by carrier number fluctuation (CNF) around threshold voltage operation, while for the p-channel transistors, a pronounced increase in the noise power spectral density is observed at higher gate voltage overdrives. This is due to the impact of the access region to the flicker noise. While the CNF noise is roughly one decade higher for the n-channel than for the p-channel transistors, the opposite holds for the access-related component for both IM and JL GAA NWFETs. It is, finally, observed that the CNF noise is on the average slightly lower in the JL devices compared with their IM counterparts; the origin of this trend will be discussed.

Modeling and simulation of the charge trapping component of BTI and RTS

Charge trapping phenomena is known to be a major reliability concern in modern MOSFETS, playing a significant role in aging through Bias Temperature Instability (BTI) and dominating low-frequency noise behavior. An electrical level modeling and simulation approach, valid at DC, AC and transient operation conditions is presented. Detailed statistical analysis is provided, aiming at proper modeling of BTI and noise variability, as well as to facilitate the understanding of physical mechanisms behind BTI and noise that are difficult to obtain otherwise. Case studies relevant for practical applications and understanding of the basic mechanisms are presented and critically discussed.

Modeling and characterization of the low frequency noise behavior for amorphous InGaZnO thin film transistors in the subthreshold region

An analytical model of the low-frequency noise (LFN) for amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) in the subthreshold region is developed. For a-IGZO TFTs, relations between the device noise and the subgap defects are characterized based on the dominant multiple trapping and release (MTR) mechanism. The LFN is considered to be contributed from trapping/detrapping of carriers both into the border traps and the subgap density of states (DOS). It is revealed that the LFN behavior of a-IGZO TFTs in the subthreshold region is significantly influenced by the distribution of tail states, where MTR process prevails. The 1/f α (with α < 1) spectrum of the drain current noise is also related to the characteristic temperature of the tail states. The new method is introduced to calculate the LFN of devices by extracting the LFN-related DOS parameters from the current-voltage characteristics.

Effects of trap density on drain current LFN and its model development for E-mode GaN MOS-HEMT

In this paper the drain current low-frequency noise (LFN) of E-mode GaN MOS-HEMT is investigated for different gate insulators such as SiO2, Al2O3/Ga2O3/GdO3, HfO2/SiO2, La2O3/SiO2 and HfO2 with different trap densities by IFM based TCAD simulation. In order to analyze this an analytical model of drain current low frequency noise is developed. The model is developed by considering 2DEG carrier fluctuations, mobility fluctuations and the effects of 2DEG charge carrier fluctuations on the mobility. In the study of different gate insulators it is observed that carrier fluctuation is the dominant low frequency noise source and the non-uniform exponential distribution is critical to explain LFN behavior, so the analytical model is developed by considering uniform distribution of trap density. The model is validated with available experimental data from literature. The effect of total number of traps and gate length scaling on this low frequency noise due to different gate dielectrics is also investigated.

Graphene electrode with tunable charge transport in thin-film transistors

Graphene, a single atomic layer of sp2-hybridized carbon, has immense potential as a transparent conducting material in electronic applications owing to its superior properties, including optical transparency and high conductivity. Particularly, the tunable work function of graphene enables the integration of graphene electrodes with various electronic devices. To achieve high performance in graphene-based devices, effective charge transport between the graphene electrode and the semiconducting material needs to be optimized; this is closely related to the modulation of the Schottky barrier (SB). In this study, we investigate the tunable charge transport properties as a function of graphene doping in n-channel thin-film transistors (TFTs) in terms of the electrical characteristics and low-frequency noise (LFN) behaviors. Alkali metal carbonates tuned the work function of graphene, resulting in a dramatic decrease in the SB and an improvement of the carrier injection in n-channel TFTs. The electrical performance of the TFTs was evaluated by extraction of the field-effect mobilities and ratio of contact resistance to total resistance. Furthermore, the level of contact noise created by the barrier height fluctuation and relative contribution of channel noise and contact noise in the TFTs was investigated by LFN measurements to demonstrate the tunable charge transport. Our findings therefore provide new insights into the tunable charge transport mechanism in graphene-based devices and reveal the immense potential of graphene as electrodes in high performance flexible and transparent displays.

Low-frequency noise characteristics in the MOSFETs processed in 65 nm technology**Project supported by the National Natural Science Foundation of China (Nos. 61574048, 61204112) and the Guangdong Natural Science Foundation (No. 2014A030313656).

Low-frequency noise behavior in the MOSFETs processed in 65 nm technology is investigated in this paper. Low-frequency noise for NMOS transistors agrees with McWhorter's theory (carrier number fluctuation), low-frequency noise in the sub-threshold regime agrees with McWhorter's theory for PMOS transistors while it agree with Hooge's theory (carrier mobility fluctuation) in the channel strong inversion regime. According to carrier number fluctuation model, the extracted trap densities near the interface between channel and gate oxide for NMOS and PMOS transistor are 3.94 × 1017 and 3.56 × 1018 cm−3/eV respectively. According to carrier mobility fluctuation model, the extracted average Hooge's parameters are 2.42 × 10−5 and 4 × 10−4. By consideration of BSIM compact model, it is shown that two noise parameters (NOIA and NOIB) can model the intrinsic channel noise. The extracted NOIA and NOIB are constants for PMOS and their values are equal to 3.94 × 1017 cm−3/eV and 9.31 × 10−4 V−1. But for NMOS, NOIA is also a constant while NOIB is inversely proportional to the effective gate voltage. The extracted NOIA and NOIB for NMOS are equal to 3.56 × 1018 cm−3/eV and 1.53 × 10−2 V−1. Good agreement between simulation and experimental results is achieved.

Investigation of Low-Frequency Noise in Nonvolatile Memory Composed of a Gate- All-Around Junctionless Nanowire FET

Low-frequency noise (LFN) behaviors, characterized with an SONOS-based gate-all-around junctionless nanowire (JLNW), are investigated to determine the suitability of this type of NW as a memory cell structure. LFN exhibits a 1/ $f$ -shape and is described by a carrier number fluctuation noise model. It is found that the proposed device structure shows a low level of device-to-device variation and high immunity against Fowler–Nordheim tunneling stress. Due to the centered conduction path in the JLNW device, the impact of correlated mobility fluctuations on the LFN is insignificant. The trapped charge in the nitride layer of the Silicon(Poly-Si)-oxide(SiO2)-nitride(SiN x )-oxide(SiO2)-silicon(Single-crystalline) (SONOS) device also negligibly influences the LFN. The NW width-dependence is clarified in terms of the effects of the oxide trap density and source/drain series resistance under a fresh and a programmed state.

Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( $L_{\mathrm{eff}}$ ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated.

Impact of the Effective Work Function Gate Metal on the Low-Frequency Noise of Gate-All-Around Silicon-on-Insulator NWFETs

The impact of the effective work function (EWF) gate metal on the low-frequency noise behavior of n-type gate-all-around nanowire (NW) FETs has been investigated. A clear reduction of the noise power spectral density has been observed for n-type TiAl-based EWF-metal gate NWFETs, indicating a reduction of the oxide trap density in the high- $\kappa $ dielectric. The difference in the observed trap density profiles for both types of devices can be explained by a beneficial impact of the presence of Al on the trap density in the underlying HfO2. The lower oxide trap density also explains the improvement of the maximum transconductance by $\sim 20$ % in the TiAl-based devices.

Low Frequency Noise Characterization and Signal-to-Noise Ratio Optimization for Silicon Hall Cross Sensors

In this paper, silicon-based Hall cross sensors with different device dimensions and carrier densities are designed and fabricated. Low frequency noise behavior regarding to the device dimension and carrier density of the Hall cross sensors has been successfully characterized. Based on the measured $1/f$ -dependent low frequency noise spectral density and the theoretically calculated geometrical factors using a finite-element analysis tool, the noise voltage is calculated and Hooge's constant is reliably extracted. The signal-to-noise ratio is thus calculated and experimentally verified. This paper provides a guidance for the optimal design of Hall cross sensors.

Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide**Project supported by the National Natural Science Foundation of China (Grant Nos. 61204112 and 61204116).

Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10−10 V2·Hz−1 and 2.7×10−8 V2·Hz−1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm−3·eV−1 to 6.16×1018 cm−3·eV−1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10−5 to 1.34×10−2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are −10.82 V and −31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.

(Invited) Investigations and Improvements of AlInN/GaN HEMTs Grown on Si

This paper reports our continuous efforts and achievements in understanding and improving AlInN/AlN/GaN heterostructure for high performance field-effect transistors and switching devices. AlInN/AlN/GaN high electron mobility transistors (HEMTs) with high electron mobility and low sheet resistance have been demonstrated on 6” Si(111) substrates. It is found that electron mobility of AlInN/AlN/GaN HEMTs is closely related to the presence and quality of the AlN spacer layer, which determines the dominant carrier scattering mechanism. A comparative study on the electrical characteristics of AlInN/AlN/GaN and AlGaN/GaN metal-insulator-semiconductor (MIS)-HEMTs shows that both devices exhibit similar low-frequency noise behavior and no obvious generation–recombination (g–r) noise component, implying carrier number fluctuation is the dominant noise mechanism in both structures.

Analysis of the Back-Gate Effect in Normally OFF p-GaN Gate High-Electron Mobility Transistor

This paper discusses the impact of the back-gate bias on the dc, low-frequency noise, and dynamic behavior characteristics of a p-GaN gate high-electron mobility transistor on silicon substrate. This paper is investigated to understand the physical mechanisms of the back-gate terminal modulation of normally OFF GaN power devices. When a negative backgate bias V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> voltage is applied, the 2-D electron gas channel will get closer to AlGaN/GaN heterointerface and interface scattering, such as interface roughness and alloy-disorder scattering will increases significantly, which may be responsible for the increased ON-state resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). Meanwhile, the opportunity for the capture of carriers by deep-level traps is reduced and the low-frequency noise is thereby suppressed. Under positive V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> bias, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> can be reduced but, according to capacitance-voltage measurements and carrier fluctuations extracted from the low-frequency noise spectra, the transported carriers are obviously trapped by the deep-level.

Low frequency noise behaviors in the partially depleted silicon-on-insulator device

Low frequency noise in the partially depleted silicon-on-insulator (SOI) NMOS device is investigated in this paper. The experimental results show low frequency noise behaviors are in good consistence with classical noise model. Based on McWhorter model, the low frequency noise in the SOI device results from the exchange of carriers between channel and oxide. The densities of trapped charges in the front gate oxide and buried oxide are extracted. Due to the difference between manufacture processes, the extracted density of trapped charges in the buried oxide (Nt=8×1017 eV-1·cm-3) is larger than that in the gate oxide (Nt=2.767×1017 eV-1·cm-3), and the result is in good agreement with testing result of transfer characteristics in part 2. Based on the charge tunneling mechanism, the spatial distribution of trapped charges in the gate oxide and buried oxide are extracted by using the tunneling attenuation coefficient (λ=0.1 nm for SiO2) and time constant (τ0=10-10 s), and the result also proves that the trap in buried oxide is larger than that in gate oxide. In addition, the influence of channel length on the low frequency noise in the SOI device is discussed. The variations of normalized channel current noise power spectral density with channel length are investigated at four frequencies(10 Hz, 25 Hz, 50 Hz, and 100 Hz). The experimental results show that the normalized noise power spectral density decreases linearly with the increase of channel length, which indicates the low frequency noise of SOI device is mainly caused by the flicker noise in the channel, and the contribution of source/drain contact and parasitic resistances could be ignored. Finally, the dependences of back gate voltage on the front gate threshold voltage, front channel current and front channel noise are discussed by considering the charge coupling effect. The experimental results show the measured channel current and channel noise with applying front gate voltage and back gate voltage simultaneously are larger than those with applying the front gate voltage and back gate voltage separately.

Radiation effects on the low frequency noise in partially depleted silicon on insulator transistors

The transfer characteristics and low-frequency noise behavior of partially depleted silicon on insulator n-channel metal-oxide-semiconductor transistors after γ-ray irradiation up to a total dose of 1M rad (Si) have been investigated in this paper. Due to the radiation-induced positive buried-oxide trapped charges and the interface traps, the back gate threshold voltage decreases from 44.72 to 12.88 V, and the electron field effect on mobility decreases from 473.7 to 419.8 cm2/V·s; while the sub-threshold swing increases from 2.47 to 3.93 V/dec. Based on the measurements of sub-threshold swing and the back gate threshold voltage, the variations of extracted radiation-induced buried oxide trapped charge and interface trap densities, are about 2.36×1012 cm-2 and 5.33×1011 cm-2 respectively. In addition, the normalized back gate flat-band voltage noise power spectral density is a sensitive function of radiation-induced buried oxide trapped charges and interface traps, which increases from 7×10-10 V2·Hz-1 to 1.8×10- 9 V2·Hz-1. According to the carrier number fluctuation model, the extracted trap density near the interface between channel and buried oxide increases from 1.42×1017 to 3.66×1017 cm- 3·eV-1. By considering the tunneling attenuation coefficient of the electron wave function and the tunneling depth of the electron in the buried oxide, the spatial distribution of trapped charges in the buried oxide before and after radiation are calculated and discussed.

Impact of processing and back-gate biasing conditions on the low-frequency noise of ultra-thin buried oxide silicon-on-insulator nMOSFETs

The analysis of the low-frequency noise of fully-depleted Silicon-On-Insulator (SOI) ultra-thin body and Ultra-Thin Buried Oxide (UTBOX) MOSFETs with different gate stacks, Si film thicknesses and extension architecture is performed. It was revealed that the extension architecture is the main factor affecting the drain current and low frequency noise behavior of the devices studied. It is revealed that the 1/f noise of extensionless MOSFETs appears to be higher than for standard ones, especially when the back interface is biased towards accumulation. The latter is accompanied by the lower drain current of extensionless devices in comparison to standard ones. Moreover, the Lorentzians accompanying the Linear Kink Effect that were revealed for standard MOSFETs, were not observed for extensionless devices. The latter is ascribed to the different architecture of the source/drain regions, which affect source/drain-body junctions characteristics and free charge carrier concentration.

Analysis of Low Frequency Drain Current Model for Silicon Nanowire Gate-All-Around Field Effect Transistor

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effects and compact modeling of RF noise behavior is analyzed for gate-all-around structure. Noise performance of gate-all-around transistor is investigated at high frequency band for radio frequency RF specified application and consequently low frequency noise behavior can be analyzed using drain current model. This paper shows that noise is decreasing with frequency. Higher subthreshold, lower drain induced barrier lowering DIBL, higher on-off ratio and higher noise figure at lower frequency is achieved by gate all around configuration and comparison has been done with double gate structure.

Impact of trap localization on low-frequency noise in nanoscale device

The impact of oxide trap localization concerning low-frequency noise has been investigated for nanoscale field effect transistors. Various low-frequency noise behaviors induced by uniformly/non-uniformly distributed gate oxide traps have been estimated using Monte-Carlo simulation and compared to experimental data. The noise level and variability are affected by the trap concentration and the channel area for uniformly distributed traps. Localized oxide traps induce different corner frequencies and noise variability according to the mean location and the standard deviation of traps.

Influence of surface states on the reverse and noise properties of silicon power diodes

This contribution investigates transient degradation of reverse characteristics of diodes by means of a noise measurement. This effect appears immediately after external heating or after a long time on-state polarisation of diodes (without a significant temperature growth of the device in this case). Simultaneously with the reverse characteristics degradation, the noise power measured under a low voltage DC reverse bias is influenced. The first possible cause of these effects is connected with so called slow surface states (SSS). The SSS are caused by the presence of material process induced defects in the region of a p-n junction surface termination. SSS have fundamental impact on the reverse properties of diodes and their low frequency noise behaviour. The second cause is connected with so called volume structural defects (VSD). Their origin can be ‘genetic’ (e.g. the presence of imperfection inside a silicon crystal) or they can be induced during technological processing. These defects are not repairable and under the reverse bias they will form so called ‘hot spots’ that is, places with a local high current density. Rapid and operative measurements of the noise power can reveal latent instabilities of reverse characteristics invisible during a standard inspection process during the production.