Low-dropout Voltage Regulator Research Articles

Dual active capacitive feedbacks for output capacitor-less low-dropout regulator

An output capacitor-less low-dropout (OCL-LDO) voltage regulator with dual active feedback paths is presented in this paper. The dual active feedbacks provide frequency compensation and spike voltage suppression. Two feedback loops are formed by capacitors Cc and Ca, respectively. The capacitor Ca path detects output voltage to suppress undershoot and overshoot during load transient. The frequency compensation is achieved by capacitor Cc, which helps the LDO regulator not only improve stability, but also enhance transient response without large current consumption. The total utilized capacitance values are only 1.5 pF. The proposed OCL-LDO was fabricated in 0.18 μm CMOS technology with supply voltage of 1.8 V. The LDO consumes 21 μA of quiescent current and the chip area is 0.47 mm × 0.49 mm. The measured output voltage difference is 90 mV when the load current is increased from 50 μA to 100 mA with CL= 100 pF and recovery time less than 1 μs. The power supply rejection is − 51.7 dB at 1 kHz.

Small-Area Radiofrequency-Energy-Harvesting Integrated Circuits for Powering Wireless Sensor Networks.

This study presents a radiofrequency (RF)-energy-harvesting integrated circuit (IC) for powering wireless sensor networks with a wireless transmitter with an industrial, scientific, and medical (ISM) of 915 MHz. The proposed IC comprises an RF-direct current (DC) rectifier, an over-voltage protection circuit, a low-power low-dropout (LDO) voltage regulator, and a charger control circuit. In the RF-DC rectifier circuit, a six-stage Dickson voltage multiplier circuit is used to improve the received RF signal to a DC voltage by using native MOS with a small threshold voltage. The over-voltage protection circuit is used to prevent a high-voltage breakdown phenomenon from the RF front-end circuit, particularly for near-field communication. A low-power LDO regulator is designed to provide stable voltage by using zero frequency compensation and a voltage-trimming feedback. Charging current is amplified N times by using a current mirror to rapidly and stably charge a battery in the proposed charger control circuit. The obtained results revealed that the maximum power conversion efficiency of the proposed RF-energy-harvesting IC was 40.56% at an input power of −6 dBm, an output voltage of 1.5 V, and a load of 30 kΩ. A chip area of the RF-energy-harvesting IC was 0.58 × 0.49 mm2, including input/output pads, and power consumption was 42 μW.

Smart power management with combined current-feedback low-dropout voltage regulator and switched capacitor DC-DC converter in 180 nm CMOS

Achieving high efficiency over a wide range of input voltages for digital signal processing modules is a key focus in integrated electronic system applications. This paper proposes a current-feedback low-dropout (LDO) voltage regulator functioning in parallel with a step-down switched capacitor DC-DC converter to implement a smart power management in 180 nm CMOS technology. The proposed switched capacitor DC-DC converter is divided into four cell to reduce the output voltage ripple. The smart power management delivers a 0.71 V power supply with an efficiency as high as 69.4% while maintaining tolerable ripple, and operates over a wide input voltage range of 1.1 V–3.0 V while occupying only 1.5 mm2. The highest value of ripple is only 14 mV. Measurement results confirm that the proposed implementation achieves a higher efficiency and wider input voltage range than conventional implementations.

A low quiescent current low dropout voltage regulator with self-compensation

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (I load ) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As I load slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the I load . On top of that, a self-compensation circuit technique is proposed where loop stability is self-attained when I load reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at I load zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.

A low quiescent current low dropout voltage regulator with self-compensation

This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.

On and Off Chip Capacitor Free, Fast Response, Low Drop-out Voltage Regulator

A low drop-out [LDO] voltage regulator with fast transient response which does not require capacitor for proper operation is proposed in this paper. Recent cap-less LDOs do not use off chip capacitor but instead they use on chip capacitor which occupy large area on chip. In the proposed LDO this on chip capacitor is also avoided. A novel secondary local feed-back technique is introduced which helps to achieve a good transient response even in the absence of output capacitor. Further a self compensating error amplifier is selected to eliminate the need of compensating capacitor. Stability analysis shows that the proposed LDO is stable with a phase margin of 78 0 . The proposed LDO is laid out using Cadence spectre in 180 nm standard CMOS technology. Post layout simulation is carried out and LDO gives 6mV/V and 360μV /mA line and load regulation respectively. An undershoot of 120 mV is observed during the load transition from 0 mA to 50 mA with 1 μs transition time, however LDO is able to recover within 1.4μs. Since capacitor is not required in any part of design, it occupies only 0.010824 mmXmm area on chip.

A Dual-Mode RF Power Harvesting System With an On-Chip Coil in 180-nm SOI CMOS for Millimeter-Sized Biomedical Implants

In this paper, we present a dual-mode power harvesting system for millimeter-sized biomedical implants that are immune to the variation of wireless link parameters and loading. The design includes a multistage full-wave voltage rectifier, a power management unit, and a low dropout voltage regulator. Depending on the received RF power level and the required power by the load, power delivery is conducted in a continuous or duty-cycled mode. The system is fabricated in 180-nm silicon on insulator (SOI) CMOS technology with an active area of 2.56 mm2 including an on-chip coil. RF power is transferred to the chip from a $2\times 2$ cm2 coil through 10 mm of air at 434 MHz. The efficiency of the designed wireless link, which is the power transfer efficiency from the external coil to the on-chip coil, reaches up to 0.68% (−21.7 dB) at 10-mm separation through air. Keeping the transmitted RF power below 24 dBm, the system can provide a 1.08-V dc voltage for resistive loads larger than 20 $\text{k}\Omega $ continuously over time. When the harvested power is not enough to drive the load continuously, the system operates in the duty-cycled mode. Measurement results show that the system can drive a 1- $\text{k}\Omega $ load in the duty-cycled mode when the transmitted power level is 15 dBm.

Self-Powered Wireless Sensor for Fault Diagnosis of Wind Turbine Planetary Gearbox

This paper proposes a wind turbine planetary gearbox (PGB) fault diagnosis method based on a self-powered wireless sensor. The proposed wireless sensor, which consists of a piezoelectric energy harvester, a power management circuit, a microcontroller unit (MCU), a radio-frequency (RF) module, and an accelerometer, can acquire the vibration signals of wind turbine PGB by the accelerometer. The piezoelectric energy harvester utilizing vibration environment is optimized as a power supply for the proposed wireless sensor, including the MCU, RF module, and accelerometer. An ac–dc converter combined with a low-dropout voltage regulator is developed to provide stable dc voltage for the proposed wireless sensor. Stacked denoising autoencoder (SDAE) shows excellent performance in learning robust features from the noised signal. Thus, in this paper, the SDAE method is adopted to learn robust and distinguishable features from measured signals. Then, the least squares support vector machine (LSSVM) is employed to classify features extracted by the SDAE. Both the SDAE and LSSVM are optimized by quantum particle swarm optimization (QPSO). The experimental results show that the presented power supply can generate 3.3-V dc voltage, which ensures regular operation of the rest of the wireless sensor. The proposed wireless sensor can achieve a reliable communication distance of 40.8 m in the test environment. Furthermore, the SDAE approach and LSSVM show excellent performance in feature extraction and fault diagnosis, respectively. The experimental results indicate that the proposed method is effective in terms of fault diagnosis for the wind turbine PGB.

A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off

A scan-reconfigurable hybrid low dropout (LDO) macro with four operating modes to support tuning across a wide range of power supply noise rejection and power efficiency is presented. The configurations include: 1) a full-digital LDO; 2) an analog loop in parallel with a digital loop in switched mode control; 3) an analog LDO in parallel with discrete current sources; and 4) discrete current sources with an analog LDO in shunt with the load. Measurements on a 130-nm CMOS test chip show a wide power supply noise rejection range of −9 dB to −34 dB and a corresponding power efficiency range of 87% to 56%.

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm2. Post layout simulations show better performance compared with other reported techniques.

Computer Simulation Model for Evaluation of Radiation and Post-Irradiation Effects in Voltage Regulator with Vertical PNP Power Transistor

The aim of the presented research was to develop a faithful SPICE simulation model of radiation and post-irradiation effects in a low-dropout voltage regulator with a vertical serial PNP transistor. The main parameters for the analysis of the circuit’s radiation response were the voltage regulator’s maximum output current and the minimum dropout voltage, as well as the serial transistor’s excess base current. All the data, comprised of the old irradiation and new annealing results, were unified and normalised, in order to enable a broad insight in the radiation tolerance of the examined circuits. Initial radiation effects, as well as the late post-irradiation effects, were successfully simulated using the variations of the maximum forward emitter current gain and knee current of the serial PNP power transistor. Ten-year room temperature annealing led to a significant recovery of the serial transistor’s excess base current, yet the maximum output current and minimum dropout voltage, in most cases, expressed further degradation. On the other hand, two short-term, high-temperature annealing periods led to the tremendous recovery of all of the irradiated voltage regulators, reducing the circuit degradation down to the level perceived after absorption of nearly 10% of the total ionising dose.

Low Dropout Based Noise Minimization of Active Mode Power Gated Circuit

Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in active mode and noise is analyzed. The effect of different noise minimization approaches for reducing power supply noise is evaluated in power gating architecture. A new concept of noise minimization technique using Low Dropout Voltage regulator is proposed in this paper. The amount of charge in the internal nodes of the power gating circuit passes through the sleep transistors during the wake-up transition is controlled by the proposed noise minimization techniques. The Low Dropout Voltage Regulator is designed newly in such a way that can be used to reduce bounce noise by minimizing voltage fluctuation on the power rail of power gating circuit. Architectures have been developed in Synopsys Custom Designer tool at iPDK 90nm technology. Percentage saving of noise on the power supply is reduced up to 99%.

Cryogenic low-dropout voltage regulators for stable low-temperature electronics

To enable scalable quantum computers, it has been proposed that the quantum–classical interface has to be integrated and operated at deep-cryogenic temperatures. Common to all electronics is the power management and distribution through the system. These systems are currently powered from room temperature supplies, thus requiring long interconnects. This results in a significant and fluctuating voltage drop from the supply to the electronics. Especially sensitive systems, such as analog-to-digital and digital-to-analog converters that are needed for the read-out and control of the quantum processor, are thus limited in performance by the stability of the voltage regulation at room temperature.In this paper, we propose the design and use of voltage regulators at cryogenic temperatures (down to 4 K), close to the actual load. As no commercial regulator was found to work below 90 K, we implemented an ad hoc low-dropout regulator with commercially available components that operate at 4 K. Its output voltage varies with less than 0.2% over the complete temperature range and it can regulate loads within 1 mV/A.

A 0.18 μm CMOS LDO Regulator for an On-Chip Sensor Array Impedance Measurement System.

This paper presents a fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator specifically designed to meet the stringent requirements of a battery-operated impedance spectrometry multichannel CMOS micro-instrument. The proposed LDO provides a regulated 1.8 V voltage from a 3.6 V to 1.94 V battery voltage over a −40 °C to 100 °C temperature range, with a compact topology (<0.10 mm2 area) and a constant quiescent current of only 7.45 μA with 99.985% current efficiency, achieving remarkable state-of-art Figures of Merit (FoMs) for the regulating–transient performance. Experimental measurements validate its suitability for the target application, paving the way towards the future achievement of a truly portable System on Chip (SoC) platform for impedance sensors.

Digital LDO modelling techniques for performance estimation at early design stage

This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.

Using the Octagonal Layout Style to Implement the Pass MOSFET to Improve the Electrical Performance of the CL–LDO Voltage Regulator

This paper presents a study by SPICE simulations and experimental data of a capacitor-less low-dropout (CL–LDO) voltage regulator (VR) by using a novel backend technique to improve its electrical performance. This study regards the use of an octagonal layout style in the pass device MOSFET of a CL–LDO VR to mainly boost its open-loop voltage gain and reduce output impedance. The results show that this innovative layout approach used in the CL–LDO voltage regulator can increase its power supply rejection ratio (PSRR) in approximately 2 dB (60 Hz), without degrading its quiescent current (Iq) (improvement of 2% better), and without wasting additional die area, in comparison to the one that its pass MOSFETs was implemented by using standard rectangular layout style. The 130 nm Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) manufacturing process from GlobalFoundries was used to implement both CL–LDO VRs, via MOSIS Educational Program. The die areas of each CL–LDO VRs are the same and equal to 0.00994mm2.

Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits

Switched-mode-control (SMC) is a control methodology that allows instantaneous switching between controllers to extend the dynamic range of feedback circuits. A hybrid low dropout voltage regulator utilizing SMC is designed in 130 nm CMOS for fine-grain power management, fast droop recovery, and accurate voltage regulation of digital load circuits. The design provides an optimal tradeoff between performance and accuracy by switching between a digital and an analog control loop. Measurements from the test-chip show near-threshold-voltage operation, peak transient response of 0.71 ns/mA, and a peak current efficiency of 98.64%.

A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control

This paper presents a recursive digital low-dropout (RLDO) regulator that improves response time, quiescent power, and load regulation dynamic range over prior digital LDO designs by 1–2 orders of magnitude. The proposed RLDO enables a practical digital replacement to analog LDOs by using an SAR-like binary search algorithm in a coarse loop and a sub-LSB pulse width modulation duty control scheme in a fine loop. A proportional-derivative compensation scheme is employed to ensure stable operation independent of load current, the size of the output decoupling capacitor, and clock frequency. Implemented in 0.0023 mm2 in 65 nm CMOS, the 7-bit RLDO achieves, at a 0.5-V input, a response time of 15.1 ns with a figure of merit of 199.4 ps, along with stable operation across a 20 000 $\times $ dynamic load range.

A Novel Passive Wireless Sensing Method for Concrete Chloride Ion Concentration Monitoring.

In this paper, a novel approach for concrete chloride ion concentration measuring based on passive and wireless sensor tag is proposed. The chloride ion sensor based on RFID communication protocol is consisting of an energy harvesting and management circuit, a low dropout voltage regulator, a MCU, a RFID tag chip and a pair of electrodes. The proposed sensor harvests energy radiated by the RFID reader to power its circuitry. To improve the stability of power supply, a three-stage boost rectifier is customized to rectify the harvested power into dc power and step-up the voltage. Since the measured data is wirelessly transmitted, it contains miscellaneous noises which would decrease the accuracy of measuring. Thus, in this paper, the wavelet denoising method is adopted to denoise the raw data. Besides, a monitoring software is developed to display the measurement results in real-time. The measurement results indicate that the proposed passive sensor tag can achieve a reliable communication distance of 16.3 m and can reliably measure the chloride ion concentration in concrete.

Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators

Low-dropout (LDO) regulators are becoming a part of modern processor architectures for fine-grain power management and higher energy efficiency. This paper shows that these integrated LDOs can also be leveraged to enhance side-channel analysis resistance of encryption engines to power side-channel analysis (PSCA) attacks. The current transformation induced by integrated LDOs coupled with limited bandwidth of the feedback loop help suppress the side-channel leakage. The impact of both analog LDO (ALDO) and all-digital LDO (ADLDO) on the load currents is studied with correlation analysis between the load and the LDO input current. The effectiveness of integrated LDOs as countermeasure to PSCA is further explored with Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA) performed on both simulated as well as measured load currents for a 128-bit Advanced Encryption Standard (AES) implemented in GF-130-nm process technology. We show that integrated LDOs can enhance PSCA resistance; however, the trade-off between integrated LDO performance and side-channel security is essential. We design integrated LDOs optimized for low-power/compact encryption engines and show that LDO-based protection can increase power attack resistance by >800× with minimal power, area, and performance overheads.