Abstract
This paper presents a fully integrated 0.18 μm CMOS Low-Dropout (LDO) Voltage Regulator specifically designed to meet the stringent requirements of a battery-operated impedance spectrometry multichannel CMOS micro-instrument. The proposed LDO provides a regulated 1.8 V voltage from a 3.6 V to 1.94 V battery voltage over a −40 °C to 100 °C temperature range, with a compact topology (<0.10 mm2 area) and a constant quiescent current of only 7.45 μA with 99.985% current efficiency, achieving remarkable state-of-art Figures of Merit (FoMs) for the regulating–transient performance. Experimental measurements validate its suitability for the target application, paving the way towards the future achievement of a truly portable System on Chip (SoC) platform for impedance sensors.
Highlights
Especially those based on bio and nano-materials, rely on Impedance Spectroscopy (IS) to evaluate their activity, i.e., the sensor information is obtained from its impedance extraction over a specific interval of stimulus frequencies [1,2,3]
One appropriate low-voltage low-power (LVLP) compatible measurement solution is the use of the Frequency Response Analysis (FRA) or lock-in amplifier-based (LIA) technique that allows using basically two quadrature phase mixers to extract the magnitude and phase information of very small sensor signals at a reference frequency f0 even in noisy environments [12]
The Vdo remains over 140 mV and, in the linear region, the output voltage experiences a maximum variation of 20 mV
Summary
Especially those based on bio and nano-materials, rely on Impedance Spectroscopy (IS) to evaluate their activity, i.e., the sensor information is obtained from its impedance extraction over a specific interval of stimulus frequencies [1,2,3]. The trend towards the integration of sensor arrays to permit multi-parameter sensor fusion and improve measurement accuracy imposes even more demanding design restrictions on the electronic circuits of the IS interface These sensor output signals present a low signal-to-noise ratio (SNR), making necessary the use of special techniques for the extraction of the information [9,10,11]. The challenge in CMOS LDO design is to achieve stability with reasonable on-chip compensation capacitance and minimum quiescent current while exhibiting good static regulating performance and fast transient behavior, since trade-offs between these parameters are interrelated. With our design specifications, we have adopted a strategy that relies on using the simplest high-gain error amplifier, a telescopic structure which will be detailed to achieve good regulating performance and PSR while simplifying stability to the two-pole case, with a minimum-area minimum-quiescent-current solution, our two critical design requirements.
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
