Low-density Parity-check Decoder Research Articles

Dual Threshold Self-Corrected Minimum Sum Algorithm for 5G LDPC Decoders

Fifth generation (5G) is a new generation mobile communication system developed for the growing demand for mobile communication. Channel coding is an indispensable part of most modern digital communication systems, for it can improve the transmission reliability and anti-interference. In order to meet the requirements of 5G communication, a dual threshold self-corrected minimum sum (DT-SCMS) algorithm for low-density parity-check (LDPC) decoders is proposed in this paper. Besides, an architecture of LDPC decoders is designed. By setting thresholds to judge the reliability of messages, the DT-SCMS algorithm erases unreliable messages, improving the decoding performance and efficiency. Simulation results show that the performance of DT-SCMS is better than that of SCMS. When the code rate is 1/3, the performance of DT-SCMS has been improved by 0.2 dB at the bit error rate of 10 − 4 compared with SCMS. In terms of the convergence, when the code rate is 2/3, the number of iterations of DT-SCMS can be reduced by up to 20.46% compared with SCMS, and the average proportion of reduction is 18.68%.

A Flexible and High Parallel Permutation Network for 5G LDPC Decoders

Cyclic shifting is usually applied in quasi-cyclic low-density parity-check (QC-LDPC) decoders for permutation operations. In this brief, we propose a flexible and high parallel permutation network for QC-LDPC decoders in the 5th generation (5G) communication systems, which supports LDPC codes with arbitrary code lengths and all lifting sizes in 5G standards. The proposed permutation network can cyclically shift at most 128 frames of data in parallel, which greatly improves the hardware efficiency and decoding throughput. Based on the TSMC 90-nm CMOS technology, synthesis results illustrate the superiority of the proposed design.

ECCPoW: Error-Correction Code based Proof-of-Work for ASIC Resistance

Bitcoin is the first cryptocurrency to participate in a network and receive compensation for online remittance and mining without any intervention from a third party, such as financial institutions. Bitcoin mining is done through proof of work (PoW). Given its characteristics, the higher hash rate results in a higher probability of mining, leading to the emergence of a mining pool, called a mining organization. Unlike central processing units or graphics processing units, high-cost application-specific integrated circuit miners have emerged with performance efficiency. The problem is that the obtained hash rate exposes Bitcoin’s mining monopoly and causes the risk of a double-payment attack. To solve this problem, we propose the error-correction code PoW (ECCPoW), combining the low-density parity-check decoder and hash function. The ECCPoW contributes to the phenomenon of symmetry in the proof of work (PoW) blockchain. This paper proposes the implementation of ECCPoW, replacing the PoW in Bitcoin. Finally, we compare the mining centralization, security, and scalability of ECCPoW and Bitcoin.

Probabilistic Shaping 44QAM Based on Many-to-One Mapping in DMT-WDM-PON

We introduce a probabilistic shaping (PS) 44-ary quadrature amplitude modulation (44QAM) based on many-to-one (MTO) mapping into a discrete multi-tone wavelength division multiplexing passive optical network (DMT-WDM-PON) with maximum shaping gain of 0.46 dB. A low-density parity-check (LDPC) based bit-interleaved coded modulation and iterative decoding system is proposed to generate and transmit the PS-44QAM DMT signal without any extra PS redundancy. An extrinsic information (EI) is iteratively used between LDPC decoder and PS demapper to retrieve the PS-44QAM DMT signal including overlapped/ambiguous symbols. The experimental results show that the PS-44QAM DMT signal with improved receiver power sensitivity and system fiber nonlinear effect tolerance can be obtained in the power splitter based WDM-PON. Thus, the corresponding system loss budget can be significantly enlarged in the optical distribution network for the purpose of serving more optical network units.

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10−7). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm2, power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm2 and 10.2 pJ/bit, respectively.

A Threshold-Based Min-Sum Algorithm to Lower the Error Floors of Quantized LDPC Decoders

For decoding low-density parity-check (LDPC) codes, the attenuated min-sum algorithm (AMSA) and the offset min-sum algorithm (OMSA) can outperform the conventional min-sum algorithm (MSA) at low signal-to-noise-ratios (SNRs), i.e., in the “waterfall region” of the bit error rate curve. This paper demonstrates that, for quantized decoders, MSA actually outperforms AMSA and OMSA in the “error floor” region, and that all three algorithms suffer from a relatively high error floor. This motivates the introduction of a modified MSA that is designed to outperform MSA, AMSA, and OMSA across all SNRs. The new algorithm is based on the assumption that trapping sets are the major cause of the error floor for quantized LDPC decoders. A performance estimation tool based on trapping sets is used to verify the effectiveness of the new algorithm and also to guide parameter selection. We also show that the implementation complexity of the new algorithm is only slightly higher than that of AMSA or OMSA. Finally, the simulated performance of the new algorithm, using several classes of LDPC codes (including spatially coupled LDPC codes), is shown to outperform MSA, AMSA, and OMSA across all SNRs.

Error Floor Estimation of LDPC Decoders — A Code Independent Approach to Measuring the Harmfulness of Trapping Sets

The linear state-space model is a well-known code-independent method to estimate the contribution of a trapping set (TS) structure to the error floor of low-density parity-check (LDPC) codes. In this paper, we provide an in-depth analysis of this method by incorporating a more accurate model for the incoming messages to the TS structure that takes into account the randomness and the correlation among such messages. Based on this analysis, we demonstrate that both randomness and correlation result in the over-estimation of the failure probability of the TS. We then propose an alternate code-independent technique for the error floor estimation of iterative LDPC decoders that can accurately estimate the contribution of different TS structures in the error floor. Compared to the linear state-space model, the proposed method is not only more accurate, but also more general, in that, it is applicable to any saturating iterative message-passing decoder, symmetrically quantized or unquantized, over any memoryless binary-input output-symmetric channel. The proposed technique can be viewed as the local application of importance sampling (IS) to the message-passing algorithm over the subgraph induced by the TS in the code’s Tanner graph. In the message-passing process, to account for the effect of the rest of the Tanner graph, density evolution along with a simple correlation model is used to generate the messages coming into the TS from the rest of the Tanner graph. Extensive simulations demonstrate that the proposed technique can accurately estimate the error floor of LDPC codes over both additive white Gaussian noise (AWGN) channel and binary symmetric channel (BSC), for a variety of iterative decoding algorithms and quantization schemes.

A Discrete Detection and Decoding of MLC NAND Flash Memory With Retention Noise

The retention noise in MLC NAND flash memory has a great impact on reliability and lifetime of devices. How to recover information from the data corrupted by retention noise is a challenging problem. The joint processing of channel estimation, detection and low-density parity-check (LDPC) decoding is an effective method to handle this problem, while which is hindered by the limited computational resource of NAND flash memory devices. This paper proposes a discrete retention-failure recovery method, where the reading system only processes integers. The proposed method consists of two major components referred to binary tree searching (BTS) based channel updating and information bottleneck (IB) based LDPC decoding. In channel updating, the proposed learning based BTS algorithm can acquire reference voltages directly; thus it bypasses the intermediate stage of retention noise parameter estimation. The LDPC decoder is realized by IB based message passing, where node operation is achieved by lookup tables, and the messages passed between nodes are integers. Besides, a dynamic quantization level reduction strategy for IB based decoding is proposed to reduce the memory consumption of lookup tables. Finally, using PEG-constructed regular LDPC code (8000, 7200), the numerical results show that the proposed discrete method has much lower computational complexity and similar performance compared with the conventional method.

Network coding schemes with efficient LDPC coded MIMO–NOMA in two‐way relay networks

The combination of non-orthogonal multiple access (NOMA) and multi-input multi-output (MIMO) approaches has been considered as assuring multiple access for the fifth generation technology. In this study, the performance of a 2 × 2 MIMO–NOMA system with low-density parity check (LDPC) codes is investigated. Redundancy with randomly interleaved differential encoding (R-RIDE) is proposed and applied to LDPC encoded messages by two users. LDPC decoding is done using the sum-product algorithm (SPA), which has two types of decoding methods, hard-decision and soft-decision. For hard-decision, bit-flipping decoder is used and for soft-decision, probability domain, log-domain, and simplified log-domain decoders are used. Bit error rate (BER) versus signal-to-noise ratio (SNR) in (dB) and average mutual information (AMI) in (bps/Hz) versus SNR (dB) are evaluated to compare the performance of the proposed and conventional LDPC schemes in NOMA and MIMO–NOMA systems. Simulation results show that both AMI and BER of the proposed LDPC–R-RIDE in MIMO–NOMA system greatly outperforms conventional LDPC coded schemes in NOMA and MIMO–NOMA systems. Moreover, the proposed R-RIDE-LDPC in MIMO-NOMA system outperforms the proposed scheme in the NOMA system. From the simulation results, LDPC–R-RIDE with simplified log-domain decoder has the best AMI result and BER performance compared with other decoding methods.

Sensor’s data transmission with BPSK using LDPC (Min-Sum) error corrections over MIMO channel: Analysis over RMSE and BER

Low-Density Parity Check (LDPC) code meets the desired performance for extended code lengths and binary fields. LDPC codes offer noteworthy error correction performance and also increase the design overhead for wireless communication systems. LDPC codes can offer proximity to Shannon Limit performance, when execution complexity and latency are not system boundaries, by using large code lengths and ever-increasing the number of iterations in the decoding process. Here in this paper, we have demonstrated data reduction method using Principal Component Analysis (PCA) for fuse data at sensor level to transmit and regress the same at the receiver for improvising the channel capacity of the system. We have fused 45 signals sensor data having a bandwidth from 50 Hz to 2500 Hz, sampled at 5 KHz each. The regression is measured using the RMSE between the transmitted and received signals. Also, the communication system has demonstrated the BER performance of the 2-Phase shift keying (BPSK) modulation technique with and without LDPC decoder (Min-Sum) for 2 × 2, 3 × 3, 4 × 4 Multiple Input Multiple Output (MIMO) channel. The performance parameters for data regression and data communication error is evaluated over AWGN channel ranging from −15 dB to 40 dB SNR. The proposed system is useful for the next generation low bandwidth communication system such as wireless systems developments, i.e., WiMAX and 4G, 5G, 6G.

Transmitting extra bits by rotating signal constellations

In this Letter, the authors propose a novel low-density parity-check (LDPC) coding scheme to transmit extra bits aided by rotated signal constellations without any additional cost in transmission power or bandwidth. In the proposed scheme, the LDPC coded data are modulated by a rotated two-dimensional signal constellation, in which the rotation angle is specified by the given extra bits. At the receiver, the rotation angle is estimated with the aid of the statistical learning of the syndrome of the LDPC code. After recovering the rotation angle, the coded payload data can be decoded by the LDPC decoder. The simulation results show that, for an LDPC code of length 2304, up to four extra bits can be transmitted with negligible influence on the reliability of the LDPC coded data.

Decoding Rate-Compatible 5G-LDPC Codes With Coarse Quantization Using the Information Bottleneck Method

Increased data rates and very low-latency requirements place strict constraints on the computational complexity of channel decoders in the new 5G communications standard. Practical low-density parity-check (LDPC) decoder implementations use message-passing decoding with finite precision, which becomes coarse as complexity is more severely constrained. In turn, performance degrades as the precision becomes more coarse. Recently, the information bottleneck (IB) method was used to design mutual-information-maximizing mappings that replace conventional finite-precision node computations. As a result, the exchanged messages in the IB approach can be represented with a very small number of bits. 5G LDPC codes have the so-called protograph-based raptor-like (PBRL) structure which offers inherent rate-compatibility and excellent performance. This paper extends the IB principle to the flexible class of PBRL LDPC codes as standardized in 5G. The extensions include IB decoder design for puncturing and rate-compatibility. In contrast to existing IB decoder design techniques, the proposed decoder can be used for a large range of code rates with a static set of optimized mappings. The proposed construction approach is evaluated for a typical range of code rates and bit resolutions ranging from 3 bit to 5 bit. Frame error rate simulations show that the proposed scheme always outperforms min-sum decoding algorithms and operates close to double-precision sum-product belief propagation decoding. Furthermore, alternatives to the lookup table implementations of the mutual-information-maximizing mappings are investigated.

3D EXIT Charts for Analyzing the 5G 3GPP New Radio LDPC Decoder

Low Density Parity Check (LDPC) codes have been selected to provide channel coding for data in the next generation of wireless communication standard referred to in practice as the 3GPP New Radio (NR). In contrast to the LDPC codes adopted in previous standards, the NR LDPC code can be considered to be a concatenation of a core LDPC code and a Low Density Generator Matrix (LDGM) code. This particular feature has the advantage of offering flexible coding rate, but it prevents the application of conventional extrinsic information transfer (EXIT) chart analysis. This article characterizes this problem and addresses it using a novel reinterpretation of the NR LDPC factor graph. Based on this factor graph, a novel 3D EXIT chart technique is conceived for our three-stage scheme, which facilitates the visual characterisation of the NR LDPC decoder's iterative decoding convergence process for the first time. The proposed EXIT chart analysis accurately visualizes the mutual information exchange amongst the components of the NR LDPC decoder, which was not facilitated by the conventional 2D EXIT chart. We demonstrate the power of this technique by using it to design a novel iterative decoding activation order for the NR LDPC decoder, which reduces the decoding complexity by approximately 17% compared to a conventional flooding decoder. This is achieved without degrading its error correction capability. We conclude by discussing several other opportunities for exploiting the proposed 3D EXIT chart technique to improve the design of concatenated LDPC and LDGM codes.

On Design of Protograph LDPC Codes for Large-Scale MIMO Systems

Protograph low-density parity-check (LDPC) codes and large-scale multi-input multi-output (LS-MIMO) systems have achieved great interest with various practical applications. However, how to effectively evaluate and design protograph LDPC codes for LS-MIMO systems remains a challenging yet critical problem, especially for low-latency applications. To solve that design challenge, the protograph extrinsic information transfer chart (PEXIT) algorithm for LS-MIMO systems, so-called LS-MIMO-PEXIT algorithm, is first derived based on the mutual information functions of messages that are passed on the joint MIMO detection and LDPC decoding graph. The proposed LS-MIMO-PEXIT algorithm plays a vital role in the optimization process of designing new protograph LDPC codes, tailored for LS-MIMO communications systems. Experiment results demonstrate that the analytical results based on the LS-MIMO-PEXIT algorithm are in good agreement with the simulation results under various input constraints, including the coding rate, the number of decoding iterations, and the LS-MIMO configuration. On top of that, the new protograph LDPC codes designed using our LS-MIMO-PEXIT algorithm achieve a coding gain from 0.2 dB at a low coding rate to 0.4 dB at a high coding rate in comparison with the state-of-the-art protograph codes in the literature. Additionally, we incorporate the practical design experience and the theoretical analysis of mutual functions into a two-step procedure to search for protograph LDPC codes that do not have error-floor behavior at frame error rate (FER) or bit error rate (BER) as low as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> or 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> , respectively. Together with the coding gain, the error-floor-free feature of the proposed protograph LDPC codes is vitally important for future wireless networks where the ultra-reliability is one of the critical requirements.

High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

Robust BICM Design for the LDPC Coded DCO-OFDM: A Deep Learning Approach

In this paper, a deep learning (DL) approach for enhancing the bit-interleaved coded modulation (BICM) receiver is designed to mitigate the clipping distortion in the low-density parity-check (LDPC) coded direct current-biased optical orthogonal frequency division multiplexing (DCO-OFDM) systems. This work aims to combine the neural network (NN) with the physical layer communications by using a model-driven DL architecture. We first develop a non-iterative NN-aided BICM (NN-BICM) receiver, where the NN is trained with the loss function of cross-entropy to output the modified conditional probability through the softmax activation function, thereby assisting in a log-likelihood ratio (LLR) improvement. Then, we propose two iterative NN-BICM receivers for iterative demapping and decoding. The single iterative design feeds the soft decisions from the LDPC decoder back to the demapper only, while the joint iterative design feeds the soft decisions back to the demapper and NN jointly. By adopting the iteration-wise pre-training strategy, the joint iterative design has been improved by representing the intractable relationship between the conditional probability and the a priori probability with a deeper NN architecture. We further investigate an efficient bit loading algorithm for DCO-OFDM systems employing the NN-BICM receiver. Both NN-BICM receivers and iterative schemes can obtain remarkable performance gains over the existing benchmarks.

A Low Complexity Decoding Scheme for Raptor-Like LDPC Codes

Recently, a new structure of low density parity check (LDPC) code named raptor-like LDPC code has attracted much attention. It has better performance at low code rate. In this paper, a novel decoding scheme for raptor-like LDPC code is proposed. First, the Gaussian approximation density evolution (GADE) algorithm is used to track and analyze the message transmission during the decoding process. It is found that certain log likelihood ratio (LLR) messages can be approximated by “zero” setting in the early iteration of raptor-like LDPC decoding. In other words, some column and row operations could be eliminated without compromise the performance. Next, we propose a new decoding scheme, which can skip unnecessary column and row operations. In comparison with the traditional belief propagation (BP)-based LDPC decoding scheme, the proposed scheme can reduce the decoding complexity. Additionally, a new algorithm is developed to facilitate the selection of the early iteration number. With this novel design, the proposed decoding scheme performs almost the same as the traditional BP-based scheme. To proof the concept, the raptor-like LDPC codes in the ATSC3.0 digital TV system are used to evaluate the proposed scheme, in comparison with the traditional BP-based schemes, i.e., sum-product algorithm (SPA), offset min-sum algorithm (OMSA), and normalized min-sum algorithm (NMSA). The simulation results confirm that the proposed scheme can reduce the decoding complexity without sacrifice in performance for all SPA, OMSA, and NMSA methods. About 10% complexity reduction can be achieved. This will reduce the buttery consumption for Internet of Things (IoT) and handheld devices.

Performance Bounds and Estimates for Quantized LDPC Decoders

The performance of low-density parity-check (LDPC) codes at high signal-to-noise ratios (SNRs) is known to be limited by the presence of certain sub-graphs that exist in the Tanner graph representation of the code, for example trapping sets and absorbing sets. This paper derives a lower bound on the frame error rate (FER) of any LDPC code containing a given problematic sub-graph, assuming a particular message passing decoder and decoder quantization. A crucial aspect of the lower bound is that it is code-independent, in the sense that it can be derived based only on a problematic sub-graph and then applied to any code containing it. Due to the complexity of evaluating the exact bound, assumptions are proposed to approximate it, from which we can estimate decoder performance. Simulated results obtained for both the quantized sum-product algorithm (SPA) and the quantized min-sum algorithm (MSA) are shown to be consistent with the approximate bound and the corresponding performance estimates. Different classes of LDPC codes, including both structured and randomly constructed codes, are used to demonstrate the robustness of the approach.

DFT-Spread DMT-WDM-PON Employing LDPC-Coded Probabilistic Shaping 16 QAM

A 5 × 100-Gb/s discrete-Fourier-transform spread (DFT-spread) discrete multi-tone wavelength division multiplexing passive optical network (DMT-WDM-PON) employing low-density parity-check (LDPC) coded probabilistic shaping 16-ary quadrature amplitude modulation (PS-16 QAM) is proposed and experimentally demonstrated. We first introduce PS-16 QAM mapping scheme with 16-point constellation reshaped from 32 symbols into splitter-based DMT-WDM-PON. The DMT-WDM-PON employing PS-16 QAM can achieve superior receiver power sensitivity (RPS) and enhanced spectral efficiency (SE) compared with the unshaped one. Compatible with the forward error correction (FEC) implemented in most of the optical transponders today, an optimized bit-interleaved coded modulation iterative decoding (BICM-ID) system based on LDPC coding is proposed to encode the PS-16 QAM DMT signal without any extra shaping codes or overheads. Then the labeling optimization with the assistance of extrinsic information transfer (EXIT) chart is investigated, in which the extrinsic messages are transferred between the PS demapper and the LDPC decoder for retrieving the PS-16 QAM DMT signal. Furthermore, the experimental results show that 1.5-dB RPS improvement and 2-dB fiber nonlinear effect tolerance enhancement are respectively realized over a 20-km standard single-mode fiber (SSMF) link by using joint applications of DFT-spread scheme and PS-16 QAM mapping in proposed DMT-WDM-PON system, which can thus provide abundant system loss budget for the legacy optical distribution networks (ODNs).