A Flexible and High Parallel Permutation Network for 5G LDPC Decoders

Abstract

Cyclic shifting is usually applied in quasi-cyclic low-density parity-check (QC-LDPC) decoders for permutation operations. In this brief, we propose a flexible and high parallel permutation network for QC-LDPC decoders in the 5th generation (5G) communication systems, which supports LDPC codes with arbitrary code lengths and all lifting sizes in 5G standards. The proposed permutation network can cyclically shift at most 128 frames of data in parallel, which greatly improves the hardware efficiency and decoding throughput. Based on the TSMC 90-nm CMOS technology, synthesis results illustrate the superiority of the proposed design.