Low-cost FPGA Research Articles

An Intelligent FPGA Based Anti-Sweating System for Bed Sore Prevention in a Clinical Environment

Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient’s skin to bed surface. Based on the temperature change, the FPGA chip select the - mode (heater/cooler) and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient’s skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

An intelligent FPGA based anti-sweating system for bed sore prevention in a clinical environment

Bed sores, a common problem among immobile patients occur as a result of continuous sweating due to increase in skin to bed surface temperature in patients lying on same posture for prolonged period. If left untreated, the skin can break open and become infected. Currently adopted methods for bed sores prevention include: use of two hourly flip chat for repositioning patient or use of air fluidized beds. However, the setbacks of these preventive measures include either use of costly equipment or wastage of human resources. This paper introduces an intelligent low cost FPGA based anti-sweating system for bed sores prevention in a clinical environment. The developed system consists of bed surface implanted temperature sensors interfaced with an FPGA chip for sensing the temperature change in patient's skin to bed surface. Based on the temperature change, the FPGA chip select the-mode heater/cooler and speed of the fan module. Furthermore, an alarm module was implemented to alert the nurse to reposition the patient only if patient's skin to bed surface temperature exceeds a predefined threshold thereby saving human resources. By integrating the whole system into a single FPGA chip, we were able to build a low cost compact system without sacrificing processing power and flexibility.

NDE system for railway wheel inspection in a standard FPGA

A special NDE system built into a low-cost FPGA has been developed for detecting railway wheelflats. The system operates with the train moving at low-speed over a measuring rail. Ultrasonic surface wave pulses are sent at regular intervals and echoes are acquired and processed by the system. The variations in the round trip time-of-flight (RTOF) of the ultrasonic pulse allow to detect and quantify the flats size. The logic design optimizes the storage capabilities by keeping only the rail–wheel contact echo and its environment. For this purpose, a wheel tracking algorithm has been implemented. It allows reducing the data volume by controlling the delay time from pulse emission to the acquisition window following the running wheel. Furthermore, since signals are masked by the rail structural noise, they are processed before executing the tracking algorithm. This work presents the architecture and performance of the developed system with experimental data.

Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster

The SMILE project main aim is to build an efficient low-cost cluster based on FPGA boards in order to take advantage of its reconfigurable capabilities. This paper shows the cluster architecture, describing: the SMILE nodes, the high-speed communication network for the nodes and the software environment. Simulating complex applications can be very hard, therefore a SystemC model of the whole system has been designed to simplify this task and provide error-free downloading and execution of the applications in the cluster. The hardware–software co-design process involved in the architecture and SystemC design is presented as well. The SMILE cluster functionality is tested executing a real complex Content-Based Information Retrieval (CBIR) parallel application and the performance of the cluster is compared (time, power and cost) with a traditional cluster approach.

Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics

Abstract Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially in the area of bioinformatics, algorithms implemented in PCs do not utilize all hardware functionalities provided by standard CPUs. As the demand for efficient utilization and speed up increases, this leads to a boost in the trend of implementing dedicated hardware. Hardware implementations can be done very fast and are cost effective on reconfigurable devices such as FPGAs. With 128 lowcost FPGAs residing on the COPACOBANA 5000 and in combination with a high-throughput systolic bus system, this machine therefore provides a dynamic solution for massively parallel computations with reconfigurable capabilities. This paper describes the advantages of this architecture based on the implementation of efficient solutions designed for two well-known algorithmic problems in bioinformatics: Smith-Waterman Alignment and DNA Motif Finding.

A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL

A low-jitter clock is essential to achieve high performance in a large scale system of distributed sensors. We propose to use a low cost DAC, VCXO and FPGA counter to generate distributed synchronous clocks. The new system called digital distributed synchronous clock (DDSC) can reduce the jitter to 14.6 ps, a 60% reduction from 36.5 ps in a traditional PLL. When these two clocks are used as the source for a 24-bit ADC system, the result shows that DDSC makes the total harmonic distortion (THD) decrease dramatically from -106 dB with PLL to -117 dB.

Low-Cost FPGA Implementation of Volterra Series-Based Digital Predistorter for RF Power Amplifiers

This paper presents a low-complexity and low-cost hardware implementation of a Volterra series-based digital predistorter (DPD). This is achieved by introducing two novel model complexity reduction techniques into the system, namely, lookup table assisted gain indexing and time-division multiplexing for multiplier sharing. Experimental results show that this novel DPD implementation uses much less hardware resources, but still maintains excellent performance compared to conventional approaches.

Timing-Driven Nonuniform Depopulation-Based Clustering

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

Matched DDWT ROI Compression Engine for the Imaging Particle Detector

A new multirate DDWT (Double Density Wavelet Transform) matched filter ROI (region of interest) processor for the ICARUS (Imaging Cosmic And Rare Underground Signals) particle detector [Amerio(2004)] has been designed. The ROI extraction engine is based on matched and unmatched Wiener filtering using coupled DWT and DDWT processing. High through-put image-like ICARUS detector data (160MBps data rate per crate) is able to be compressed 600 times using multi-stage compression with ROI extraction. The 32-channel (160MBps data rate) processor has been fully implemented in a low cost FPGA device thanks to Fast Integer Arithmetic Wavelet Transform (FIAWT) [Pólchlopek(2006)] algorithm implementation.

Special purpose processor for parameter identification of CNC second order servo systems on a low-cost FPGA platform

The parameter identification process has an important role in servo systems tuning on computer numerical control (CNC) machine tools. The parameter identification is mostly done off-line due to the high computational load carried by the identification algorithms. In this work, we present a novel hardware architecture for an application specific processor implementing the recursive least-squares algorithm for the on-line identification. The developed processor is simulated and tested with the necessary elements to perform the CNC machine servo system control. The system was implemented in a low-cost FPGA, getting a maximum sample frequency of 40 kSps.

Reconfigurable Self-Organizing Neural Network Design and it's FPGA Implementation

The use of Kohonen self-organizing feature maps in real time applications requires high computational performance, especially for embedded systems and hence neural network chips are essential. A digital architecture of Kohonen neural network with learning capability and on-chip adaptation and storage is proposed with the implementation of Kohonen SelfOrganizing Map (SOM) neural networks on the low-cost Spartan-3 FPGAs. The architecture of this digital chip based on the idea that some assumptions for the restrictions of the algorithm can simplify the implementation. Using the Manhattan distance, a special treatment of the adaptation factor, and neighborhood functions will decrease the necessary chip area so that a high number of processing elements can be integrated on one chip.

FPGA based Digital Pulse Width Modulator with Time Resolution under 2 ns

This work proposes a new DPWM architecture that takes advantage of FPGA’s advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.

FPGA-oriented HW/SW implementation of ECG beat detection and classification algorithm

The aim of this paper is to present an FPGA-oriented system design for ECG signal processing. The system performs QRS complex detection and beat classification into either normal or premature ventricular contractions. QRS complex detection is made with an algorithm based on a phase-space portrait of an ECG signal, while for beat classification a part of the Open Source ECG Analysis Software is used. The former is performed in HW and the latter in SW on an integrated PowerPC 405 core. The algorithm was developed on the MIT-BIH Arrhythmia Database where a QRS complex sensitivity of 99.82% and positive predictivity of 99.83% and a PVC sensitivity of 92.36% and specificity of 95.54% were achieved. The processing speed is measured and the results show that the HW/SW implementation of the algorithm processes the ECG data up to 15 times faster than the SW implementation, meaning that real-time ECG signal analysis is possible at much lower frequencies than in analysis performed in SW. We show that the HW/SW implementation makes it possible to use low-cost FPGA devices with soft-core microprocessors in systems where a high processing speed is required.

A Reliable FPGA-based Real-time Optical-flow Estimation

Optical flow is a research topic of interest for many years. It has, until recently, been largely inapplicable to real-time applications due to its computationally expensive nature. This paper presents a new reliable flow technique which is combined with a motion detection algorithm, from stationary camera image streams, to allow flow-based analyses of moving entities, such as rigidity, in real-time. The combination of the optical flow analysis with motion detection technique greatly reduces the expensive computation of flow vectors as compared with standard approaches, rendering the method to be applicable in real-time implementation. This paper describes also the hardware implementation of a proposed pipelined system to estimate the flow vectors from image sequences in real time. This design can process 768 × 576 images at a very high frame rate that reaches to 156 fps in a single low cost FPGA chip, which is adequate for most real-time vision applications.

A Software and Hardware IPTV Architecture for Scalable DVB Distribution

Many standards and even more proprietary technologies deal with IP-based television (IPTV). But none of them can transparently map popular public broadcast services such as DVB or ATSC to IPTV with acceptable effort. In this paper we explain why we believe that such a mapping using a light weight framework is an important step towards all-IP multimedia. We then present the NetCeiver architecture: it is based on well-known standards such as IPv6, and it allows zero configuration. The use of multicast streaming makes NetCeiver highly scalable. We also describe a low cost FPGA implementation of the proposed NetCeiver architecture, which can concurrently stream services from up to six full transponders.

FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set

With the constant and rapid advances in microelectronics and networking technology, network service providers' needs for tuning up services, in order to attract more subscribers, have become more important. Ethernet technology has improved in terms of communication speed and has established itself as a standard enabling more recently throughput rates in the range of 1-100 Gbps. However, the need for quality services requires Ethernet testers to be not only standard compliant, but also meet performance criteria as specified by the standard. Performance criteria are difficult to prove and typically cannot be accomplished by software due to the limitations of the underlying general purpose hardware as well as the existence of many software layers. In this paper, we propose a design, an implementation and the performance verification achievements of an Ethernet tester compliant with the throughput and latency tests specified by the RFC 2544 for 10/100 Mpbs Ethernet networks. The results showed that the device designed achieved the performance criteria defined by the RFC while it was implemented in a Commercial Off-The-Shelf (COTS) low cost FPGA board. The performance was compared to an existent software implementation and the results showed that the usual limitations added by several hardware and software layers can be overcome by implementing a frame generator, monitor and media access (MAC layer 2) directly in an FPGA device.

FPGA-Based Digital Pulsewidth Modulator With Time Resolution Under 2 ns

This paper proposes a new digital pulsewidth modulation (DPWM) architecture that takes advantage of the field-programmable gate array's (FPGA) advanced characteristics, especially the delay-locked loop (DLLs) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low-cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests.

FPGA implementation of a stochastic neural network for monotonic pseudo-Boolean optimization

In this paper a FPGA implementation of a novel neural stochastic model for solving constrained NP-hard problems is proposed and developed. The model exploits pseudo-Boolean functions both to express the constraints and to define the cost function, interpreted as energy of a neural network. A wide variety of NP-hard problems falls in the class of problems that can be solved by this model, particularly those having a quadratic pseudo-Boolean penalty function. The proposed hardware implementation provides high computation speed by exploiting parallelism, as the neuron update and the constraint violation check can be performed in parallel over the whole network. The neural system has been tested on random and benchmark graphs, showing good performance with respect to the same heuristic for the same problems. Furthermore, the computational speed of the FPGA implementation has been measured and compared to software implementation. The developed architecture featured dramatically faster computation, with respect to the software implementation, even adopting a low-cost FPGA chip.

Adaptive ADPLL architecture for MPEG system clock related measurements in variable rate environment

Measurements such as jitter, frequency offset and drift are very important in the quality of service evaluation in digital video broadcast, especially under varying rate environment. This paper presents an all digital phase locked loop (ADPLL) architecture for either VLSI or low cost FPGA implementation. The operation of proposed ADPLL is based on a frequency synthesizer for a very narrow band frequency ( ± 800 Hz), small frequency step and high central frequency (27 MHz). The proposed solution is designed for the real time measurements, feature a very low intrinsic jitter, and adaptive rate variation. The system description and adaptation method are presented with corresponding hardware implementation. Experimental results in term of jitter analysis and adaptation behavior are detailed and discussed.