Low-cost FPGA Research Articles

FPGA architecture for text extraction from images

Image processing is a computationally intensive operation and it is typically done in software using CPU processing power that is readily available these days. The applications that make use of image processing require expensive and powerful CPUs to perform real-time operations. Hence a low cost FPGA based image processing solution becomes useful. This eliminates the need for powerful CPUs and at the same time real-time processing can be achieved relatively easier. This paper proposes an algorithm for extracting text information from images. With the help of FPGA, the pixels can be pipelined or processed in parallel in order to achieve increased processing speed. The gray scale conversion is done on the input image followed by image binarization. In order to extract text from input image, morphological close operation and connected component analysis are performed. The ultimate aim and motivation of this paper is detected and extract the words and letters from the input image with efficient hardware architecture. Simulation is done using VHDL coding and the analysis and synthesis results are carried out using the device XC7VX330T of Virtex7 family. FPGA provides higher flexibility since the architecture can be easily upgraded to meet the requirement. It is observed that area and power minimization is obtained by implementing an optimized design using this algorithm.

Floating-point accelerator for biometric recognition on FPGA embedded systems

This paper aims at presenting a Floating-Point Biometric Accelerator (FPBA) specially designed to speed-up processing kernels used in biometric algorithms. The FPBA was developed in order to facilitate its inclusion as part of an embedded system that was implemented on a low-cost FPGA family from Xilinx. The advantage of this approach is that such algorithms can be programmed on the same hardware architecture following a software design flow. The internal design includes several blocks that compute basic operations and transcendental functions useful in biometrics. For comparison purposes, the execution time of four typical biometric kernels resolved by the FPBA were compared against the floating-point unit (FPU) provided by Xilinx. In all cases, the experimental results show that the FPBA reduces the execution time by a factor ranging from x7 to x22. The results also show the execution of two biometric recognition algorithms that are accelerated by x7 and x16.

Hardware accelerator IP cores for real time Radar and camera-based ADAS

The paper presents the design of HDL macrocells, working as hardware accelerators to achieve real time processing of some key functions of Advanced Driver Assistance Systems (ADAS). Particularly, the macrocells process in real time images from Radar and video-camera sensors implementing computing-intensive operations such as: pixel-level filtering, correction of distortions in large field-of-view cameras, multi-camera image fusion for panoramic view of car’s surround, traffic and road signs recognition, detection of obstacles for collision avoidance, and estimation of their distance and speed. The HDL macrocells are fully configurable and are synthesized in low-cost Artix-7 FPGA family, satisfying automotive-grade requirements. They can be integrated as accelerators in embedded hardware–software platforms to build a complete ADAS solution. To this aim, the macrocells have been synthesized also in a Zynq FPSoC. With respect to the state of the art, the proposed macrocells stand for their low-power and real time performance .

High-speed implementation of fractal image compression in low cost FPGA

Fractal image compression (FIC) is a very popular coding technique use in image/video applications due to its simplicity and superior performance. The major drawback with FIC is that it is very time consuming algorithm, especially when a full search is attempted. Hence, it is very challenging to achieve a real-time operation if this algorithm is implemented on general processors. In this paper, a new parallel architecture with bit-width reduction scheme is implemented. The hardware is synthesized on Altera Cyclone II FPGA whose architecture is optimized at circuit level in order to achieve a real-time operation. The performance of the proposed architecture is evaluated in terms of runtime, peak-signal-to-noise-ratio (PSNR) and compression efficiency. On average the speedup of 3 was attainable through a bit-width reduction while the PSNR was maintained at acceptable level. Empirical results demonstrate that this firmware is competitive when compared to other existing hardware with PSNR averaging at 29.9 dB, 5.82% compression efficiency and a runtime equivalent to video speed of 101 frames per second (fps).

A real-time stereo vision system for distance measurement and underwater image restoration

This paper presents the development of an embedded real-time system that performs distance measurement and restoration of underwater images, using stereo vision techniques. To achieve a high performance low-cost implementation, the overall system has been developed using a hardware/software codesign approach. Several hardware modules have been designed to implement the several pixel intensive tasks, such as background image storage, background subtraction, center of mass calculation, and image restoration. On the other hand, less intensive tasks, such as the estimation of the disparity and the distance tasks (performed just once for each image), are executed using an embedded soft processor (Altera Nios II). The developed platform employs a pair of identical CMOS cameras for the stereo vision system, a low-cost FPGA, and an small screen for visualization of the images. In this paper, we describe both the overall design of the system and the calibration procedure used to determine the stereo vision system parameters. The Altera Quartus II was used as a synthesis tool, which estimates that the system consumes 115.25 mW and achieves an output of 26.56 frames per second for images of $$800\times 480$$ pixels. The synthesis results and the measurement precision show that the developed system is suitable for real-time tasks.

A novel FPGA-based system for real-time calculation of the Spectral Kurtosis: A prospective application to harmonic detection

Autonomous measurement units are indispensable for the development of the smart grid in order to get faster processing responses, stability, and to provide the user with information regarding power quality (losses, harmonics, outages, steady-state and transient events). In this paper, the development of a novel FPGA-based real-time analyzer is presented. The signal processing nucleus is based on higher-order statistics, introducing the Spectral Kurtosis as an online assessment. Indeed, this fourth-order spectrum enhances non-Gaussian behavior in very unfavorable noise conditions. In the Power Quality assessment frame, the outline of this spectrum can be used to reveal the presence of underlying electrical perturbations. In this paper it is presented an autonomous analyzer that uses the Spectral Kurtosis to detect the presence of low level harmonics. These harmonics are difficult to detect using conventional techniques and can generate problems in power distribution when they are associated to a resonant response in the powered load. The proposed system has been described in synthesizable VHDL and performs an indirect estimator of a poly-spectrum slide, based on the FFT. This synthesizable description has been implemented using a low cost FPGA, enabling a continuous monitoring of the power signal (without dead times) with a high oversampling rate. The proposed solution has been conceived to be introduced in smart grids with high penetration of Distributed Energy Resources (DER).

Genome-wide Association Interaction Studies with MB-MDR and maxT Multiple Testing Correction on FPGAs

In the past few years massive amounts of data have been generated for genetic analysis. Existing solutions to analyze this data concerning genome-wide gene interactions are either not powerful enough or can barely be managed with standard computers due to the tremendous amount of statistical tests to be performed. Also, common approaches using cluster or cloud technologies for parallel analysis are operating at the edge of what is currently possible.This work demonstrates how FPGAs are able to address this problem. We present a highly parallel, hardware oriented solution for genome-wide association interaction studies (GWAIS) with MB-MDR and the maxT multiple testing correction on an FPGA-based architecture. We achieve a more than 300-fold speedup over an AMD Opteron cluster with 160 cores on an FPGA-system equipped with 128 Xilinx Spartan6 LX150 low-cost FPGAs when analyzing a WTCCC-like dataset with 500,000 markers and 5,000 samples. Furthermore, we are able to keep pace with a 256-core Intel Xeon cluster running MB-MDR 4.2.2 with an approximative version of maxT, while we achieve a 190-fold speedup over the sequential execution of this version on one Xeon core.

Development of a practical foolproof system using ultrasonic local positioning

The objective of this research is to develop a prototype for practical foolproof system which can be used in manual assembly processes. For this purpose, a high-performance and low-cost ultrasonic system is proposed to measure 3D positions of an indoor mobile object. Composed of an ultrasonic sender and a receiver, the system employs ultrasonic time-of-flight (TOF) and trilateration to estimate the positions of the object with an accuracy of few centimeters. To calculate three TOFs, ultrasonic signals are processed full-digitally with a low-cost FPGA, which provides high design flexibility keeping both high performance and low noise. Proposed system is autonomous, so there is no need of an external PC and the system development cost becomes low. As an improved thresholding method to calculate the TOFs, this paper proposes a debounce module, designed in the FPGA, to remove the pulse noises generated during the thresholding. The resulting time delay from the debounce is compensated by a microprocessor for calculating actual TOFs. Lastly, the positions of the mobile object are calculated from the TOFs values by trilateration in the microprocessor. In order to remove measurement noises, both moving average filters and Kalman filters are adopted in calculating the TOFs and positions.

Implementation of a Cross-Spectrum FFT Analyzer for a Phase-Noise Test System in a Low-Cost FPGA

The cross-correlation method allows phase-noise measurements of high-quality devices with very low noise levels, using reference sources with higher noise levels than the device under test. To implement this method, a phase-noise analyzer needs to compute the cross-spectral density, that is, the Fourier transform of the cross-correlation, of two time series over a wide frequency range, from fractions of Hz to tens of MHz. Furthermore, the analyzer requires a high dynamic range to accommodate the phase noise of high-quality oscillators that may fall off by more than 100 dB from close-in noise to the noise floor at large frequency offsets. This paper describes the efficient implementation of a cross-spectrum analyzer in a low-cost FPGA, as part of a modern phase-noise analyzer with very fast measurement time.

<monospace>STES</monospace>: A Stream Cipher Based Low Cost Scheme for Securing Stored Data

The problem of securing data present on USB memories and SD cards has not been adequately addressed in the cryptography literature. While the formal notion of a tweakable enciphering scheme (TES) is well accepted as the proper primitive for secure data storage, the real challenge is to design a low cost TES which can perform at the data rates of the targeted memory devices. In this work, we provide the first answer to this problem. Our solution, called STES, combines a stream cipher with a XOR universal hash function. The security of STES is rigorously analyzed in the usual manner of provable security approach. By carefully defining appropriate variants of the multi-linear hash function and the pseudo-dot product based hash function we obtain controllable trade-offs between area and throughput. We combine the hash function with the recent hardware oriented stream ciphers, namely Mickey, Grain and Trivium. Our implementations are targeted towards two low cost FPGAs—Xilinx Spartan 3 and Lattice ICE40. Simulation results demonstrate that the speeds of encryption/decryption match the data rates of different USB and SD memories. We believe that our work opens up the possibility of actually putting FPGAs within controllers of such memories to perform low-level in-place encryption.

System Architecture for Real-Time Face Detection on Analog Video Camera

This paper proposes a novel hardware architecture for real-time face detection, which is efficient and suitable for embedded systems. The proposed architecture is based on AdaBoost learning algorithm with Haar-like features and it aims to apply face detection to a low-cost FPGA that can be applied to a legacy analog video camera as a target platform. We propose an efficient method to calculate the integral image using the cumulative line sum. We also suggest an alternative method to avoid division, which requires many operations to calculate the standard deviation. A detailed structure of system elements for image scale, integral image generator, and pipelined classifier that purposed to optimize the efficiency between the processing speed and the hardware resources is presented. The performance of the proposed architecture is described in comparison with the detection results of OpenCV using the same input images. For verification of the actual face detection on analog cameras, we designed an emulation platform using a low-cost Spartan-3 FPGA and then experimented the proposed architecture. The experimental results show that the processing time for face detection on analog video camera is 42 frames per second, which is about 3 times faster than previous works for low-cost face detection.

A FPGA based time analyser for stochastic methods in experimental physics

A two-channel time analyser data acquisition system is developed for analysis of stochastic processes of random time interval pulses. The system is implemented on a typical low cost FPGA device. Two stochastic processes of nuclear interactions can be recorded by the system independently without any inter-channel dead time behaviour. The experimental results without any hardware based data reduction are transferred to the computer to perform arbitrary post analysis of the data using powerful software engineering tools to estimate the statistical properties of the processes. The performance of the system is verified experimentally. The maximum time digitization period and the minimum channel dead time are measured equal to 3.3 and 10 ns, respectively, using a typical prototype hardware platform. A brief description about theory of Rossi-α diagnostic method (a type of zero power reactor noise analysis) is initiated in the text as an application of the system. The method is applied to multiplying and non-multiplying media using the proposed measuring system.

AN EFFICIENT FPGA BASED SPACE VECTOR PULSE WIDTH MODULATION IMPLEMENTATION FOR SERVO CONTROL APPLICATION

This paper focuses on the design of a low power and high performance FPGA based Space Vector Pulse Width Modulation (SVPWM) controller for three phase implementation for Servo control Application. A new method is proposed to realize easy, accurate and high performance SVPWM technique based on FPGA with low resource consumption and reduced execution time than conventional methods. The FPGA based SVPWM generation involves a digital controller implementation to execute the algorithm and DQ reference generator gives reference vector signal to the controller. The controller in turn controls the PLL generator to generate pulse width modulated clock for three phases. The PLL generator is sourced by clock generator. Experimental results are presented for SVPWM architecture synthesized on standard low-cost FPGA chips, showing very good linearity and resolutions up to 1ns.

A remote islanding detection and control strategy for photovoltaic-based distributed generation systems

This study presents a new remote islanding detection method and control system for photovoltaic (PV) based Distributed Generation (DG) systems. The proposed method monitors and controls the grid, local load and the output of the PV inverter in real time with the communication of circuit breakers. The proposed remote control system detects the changes in the currents of the circuit breakers, frequency, and the voltages by checking the defined threshold values at all electrical branches of the PV system. The proposed islanding detection algorithm was implemented by a low-cost FPGA board. The control system was also designed by considering a Very Large Scale Integration (VLSI) structure. The proposed method was verified by a developed prototype PV system constituted in the laboratory. The proposed control system was checked in a resonance condition with an active power match, and the verified results indicated that the developed system was also independent of the load and the inverter. Islanding detection time is approximately 1.65ms even in a worst-case operational scenario, and this is a significantly shorter response time according to the existing standards. The proposed method presents a realistic solution to islanding, is easy to implement, and is suitable for real system applications. The method also provides a reliable islanding detection and presents a low-cost solution to the subject.

A versatile digital camera trigger for telescopes in the Cherenkov Telescope Array

This paper describes the concept of an FPGA-based digital camera trigger for imaging atmospheric Cherenkov telescopes, developed for the future Cherenkov Telescope Array (CTA). The proposed camera trigger is designed to select images initiated by the Cherenkov emission of extended air showers from very-high energy (VHE, E>20GeV) photons and charged particles while suppressing signatures from background light. The trigger comprises three stages. A first stage employs programmable discriminators to digitize the signals arriving from the camera channels (pixels). At the second stage, a grid of low-cost FPGAs is used to process the digitized signals for camera regions with 37 pixels. At the third stage, trigger conditions found independently in any of the overlapping 37-pixel regions are combined into a global camera trigger by few central FPGAs. Trigger prototype boards based on Xilinx FPGAs have been designed, built and tested and were shown to function properly. Using these components a full camera trigger with a power consumption and price per channel of about 0.5W and 19€, respectively, can be built. With the described design the camera trigger algorithm can take advantage of pixel information in both the space and the time domain allowing, for example, the creation of triggers sensitive to the time-gradient of a shower image; the time information could also be exploited to online adjust the time window of the acquisition system for pixel data. Combining the results of the parallel execution of different trigger algorithms (optimized, for example, for the lowest and highest energies, respectively) on each FPGA can result in a better response over all photons energies (as demonstrated by Monte Carlo simulation in this work).

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator

In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 × 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical.

English

In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4(N) 4-point FFTs to construct N-point FFT rather than (N/8) logs (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency

Performance evaluation of multiple (32 channels) sub-nanosecond TDC implemented in low-cost FPGA

NA62 experiment Straw tracker frontend board serves as a gas-tight detector cover and integrates two CARIOCA chips, a low cost FPGA (Cyclon III, Altera) and a set of 400Mbit/s links to the backend. The FPGA houses 16 pairs of sub-nanosecond resolution TDCs with derandomizers and an output link serializer. Evaluation methods, including simulations, and performance results of the system in the lab and on a detector prototype are presented.

Hardware Neural Networks Modeling for Computing Different Performance Parameters of Rectangular, Circular, and Triangular Microstrip Antennas

In the last one decade, neural networks-based modeling has been used for computing different performance parameters of microstrip antennas because of learning and generalization features. Most of the created neural models are based on software simulation. As the neural networks show massive parallelism inherently, a parallel hardware needs to be created for creating faster computing machine by taking the advantages of the parallelism of the neural networks. This paper demonstrates a generalized neural networks model created on field programmable gate array- (FPGA-) based reconfigurable hardware platform for computing different performance parameters of microstrip antennas. Thus, the proposed approach provides a platform for developing low-cost neural network-based FPGA simulators for microwave applications. Also, the results obtained by this approach are in very good agreement with the measured results available in the literature.