Timing-Driven Nonuniform Depopulation-Based Clustering

Hanyu Liu,Ali Akoglu

doi:10.1155/2010/158602

Abstract

Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%.

Highlights

Field-programmable gate arrays (FPGAs) were first introduced in 1980s
We examine the performance of our proposed clustering technique and explore the effects of two depopulation strategies (“Basic Logic Element (BLE)-limit” and “input-limit”)
Depopulation leads to more external connections among Configurable Logic Blocks (CLBs) and typically results with an increase in critical path delay

Summary

Introduction

Field-programmable gate arrays (FPGAs) were first introduced in 1980s. While they are less efficient than ASICs, FPGAs are becoming more popular because of their low nonrecurrent engineering cost and fast time-to-market. For the sake of routability, when nets go through longer paths, critical path delay may increase. We may solve these problems by migrating to the resourcerich FPGA device which has more routing resources by paying 7× price. In order to avoid this, FPGA CAD flow must improve the routability as well as timing performance to make the low-cost device a feasible option

Results

Discussion

Conclusion