Low-cost FPGA Research Articles

New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC

New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC

New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA

New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA

Novel Minimalist Hardware Architecture for Long Sync Word Frame Synchronization and Payload Capture

Sync word-based frame synchronization is an established method of frame synchronization that is employed in many low-resource applications because of its simplicity, and it involves the attachment of sync words (digital binary sequences) to the frames, which are then used for detection. Despite its simplicity, the method is underutilized today because there is no available hardware scheme that can perform correlation-based sync word frame synchronization with long sync words (>80 bits) efficiently. For this reason, the sync word methods that are used typically employ sync words of shorter lengths (<50 bits) with limited accuracy. This article introduces a highly modifiable, minimalist hardware architecture that performs correlation-based sync word frame synchronization using long sync words with evident accuracy gains over existing methods. As a bonus, the architecture not only detects the frame but also captures its payload regardless of size. Its low complexity allows for its deployment at a low cost in terms of hardware resources and power while providing high bit rates. Its flexibility is demonstrated by using a low-cost FPGA for implementation.

A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm

A Low Cost FPGA Implementation of Retinex Based Low-Light Image Enhancement Algorithm

Real time hybrid medical image encryption algorithm combining memristor-based chaos with DNA coding

Image encryption is a commonly used method to secure medical data on a public network, playing a crucial role in the healthcare industry. Because of their complex dynamics, memristors are often used in developing novel chaotic systems that can improve the efficiency of encryption algorithms based on chaos. In this work, we propose a novel locally active memristor-based chaotic circuit model and present a real time hybrid image encryption application developed on a PYNQ-Z1 (Python Productivity for Zynq) low-cost FPGA board using Jupiter programming environment. The proposed hybrid algorithm combines memristor-based chaos with a DNA (deoxyribonucleic acid) encryption algorithm exploiting diffusion-confusion technique. We initially present a new compact and inductorless chaotic circuit, derive the model equations, and then verify its chaotic dynamics numerically through the investigation of the phase portraits, Lyapunov exponents and the bifurcation diagrams. We further implement the chaotic circuit experimentally with discrete elements. The randomness of the chaotic sequence is improved using Trivium and von Neumann post-processor algorithms and assessed through the NIST tests. Finally, the performance of the encryption algorithm is evaluated through various metrics, including histogram and correlation analyses, differential attack, information entropy, as well as data-loss and noise attack, demonstrating its security and suitability for real-time encryption systems.

A custom discrete amplifier-shaper-discriminator circuit for the drift chambers of the R3B experiment at GSI

This contribution presents a pragmatic approach to read-out electronics for drift chambers used in particle physics experiments, specifically for the R3B experiment at GSI. The design uses discrete miniature SMD components and LVDS inputs of a low-cost FPGA to achieve a performance similar to classic ASIC solutions to the problem. The circuit comprises a high gain, low noise amplifier, a custom signal shaper, tailored to the specifics of proportional counter signals, and a leading-edge discriminator with programmable threshold. The presented approach offers an attractive solution for small to medium sized detector systems that require specialized read-out electronics but cannot afford the high cost and development effort associated with ASICs.

Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach

Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach

Low-Cost FPGA Implementation of Deep Learning-Based Heart Sound Segmentation for Real-Time CVDs Screening

Low-Cost FPGA Implementation of Deep Learning-Based Heart Sound Segmentation for Real-Time CVDs Screening

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a high-density,129-channel, dual-‘hit’ FPGA-based time-to-digital converter (TDC) developed to implement the trigger-less data acquisition (DAQ) system for the Iron Calorimeter (ICAL) detector of the India-based Neutrino Observatory (INO) experiment. In this trigger-less DAQ scheme, the arrival time of signals from all the detector channels, about 3.6 million channels in the case of the INO-ICAL experiment, is required to be measured. This work, therefore, aimed at the development of a low-power, high-density TDC with uniform performance across the channels in the low-cost Spartan-6 FPGA. This TDC is based on tapped delay line (TDL) interpolation technique built using CARRY4 elements of the FPGA in the Spartan-6 FPGA-based DAQ system. In this TDC, a method for measuring the time-of-arrival of both the rising edge and subsequent falling edge (dual-hit) using a single channel is developed, thus allowing pulse width measurements. Here, a resource and power-aware design methodology is developed to arrive at the optimum values of the total number of delay elements in the TDL and clock frequency, facilitating the implementation of a large number of identical TDC channels. Further, in order to meet the area and timing constraints of the high-density TDC, semi-automatic placement scripts are developed with careful partitioning of the TDC channels. These aspects resulted in an implementation of the TDC with a least significant bit (LSB) resolution of 84.4 ps ± 2.5 ps, a dynamic range of 40 μs, time precisions (σ) across the channels in the range of 42 ps (0.49 LSB) to 58 ps (0.68 LSB), differential nonlinearity (DNL) of ±0.5 LSB and integral nonlinearity (INL) of [-0.49,0.84] LSB with a low power consumption of 7 mW per channel.

An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture

This paper proposes a low-cost disparity map compression algorithm and its hardware architecture for high resolution and high frame rate applications. The proposed algorithm uses spatial correlations between neighboring disparities and has two variants. The first variant encodes the current disparity using its left neighbor, whereas the second variant benefits from left and upper neighbors. The proposed algorithm obtains 48% and 56% savings in memory space on the average for its variants. The proposed architecture can support 1080p resolution at 60 fps on a low-cost FPGA device while consuming very low area and power.

Field programmable gate arrays implementation of a Kalman filter based state of charge observer of a lithium ion battery pack

This paper presents a study on the state of charge observation of lithium-Ion batteries for energy management in embedded applications. The knowledge of the state of charge is fundamental for the safety and optimal usage of these batteries. The study focuses on the development and implementation of a Kalman filter-based observer algorithm on a Spartan 6 FPGA that can accurately estimate the state of charge of a battery, even if it is initialized differently from its actual state. In this paper we have focused on the opportunities of FPGA for fast calculation which allow to use the FPGA as a slave component in a BMS and allow to observe the SOC a great deal of cells with a low cost. The implementation of this observer on a low-cost FPGA can lead to cost reduction for battery management systems in various applications, such as electric cars and any other systems requiring the observation of the state of charge of a battery pack. The observer model was validated through simulations and real-time testing. This study presents a promising approach to accurately estimate the state of charge of Lithium-Ion batteries for efficient energy management in various applications.

FPGA Implementation of Shack–Hartmann Wavefront Sensing Using Stream-Based Center of Gravity Method for Centroid Estimation

We present a fast and reconfigurable architecture for Shack–Hartmann wavefront sensing implemented on FPGA devices using a stream-based center of gravity to measure the spot displacements. By calculating the center of gravity around each incoming pixel with an optimal window matching the spot size, the common trade-off between noise and bias errors and dynamic range due to window size existing in conventional center of gravity methods is avoided. In addition, the accuracy of centroid estimation is not compromised when the spot moves to or even crosses the sub-aperture boundary, leading to an increased dynamic range. The calculation of the centroid begins while the pixel values are read from an image sensor and further computation such as slope and partial wavefront reconstruction follows immediately as the sub-aperture centroids are ready. The result is a real-time wavefront sensing system with very low latency and high measurement accuracy feasible for targeting on low-cost FPGA devices. This architecture provides a promising solution which can cope with multiple target objects and work in moderate scintillation.

Practical Implementation of the Indirect Control to the Direct 3 × 5 Matrix Converter Using DSP and Low-Cost FPGA

The popularity of multiphase drives is increasing due to the growing interest in drives with more than three phases. One promising topology is the multiphase matrix converters, which enable the implementation of a single-stage AC/AC power conversion system with bidirectional power flow capability. In this paper, we present the implementation of indirect control for a practical sample of the direct matrix converter. To reduce the overall cost of the control solution for these types of converters, we utilized low-cost FPGA and DSP. The usage of only DSP itself was not possible due to low number of available PWM output needed for 3 × 5 MxC driving. Another reason is commutation, which must be precise and fast to avoid any hazardous states in the converter. Due to these problems, the authors decided to implement an algorithm of a combination of DSP and FPGA, where FPGA is used for time critical operations. The indirect algorithm treats the converter as two separate parts, the rectifier and the inverter, with the DC-LINK being fictitious. The matrix converter is composed of compact modules, and the entire system is verified. The practical verification demonstrates that matrix converters can produce a wide range of output frequencies and achieve input power factor control. Finally, we compare and review the practical model with the simulation model, examining efficiency and other parameters.

Design and Implementation of a flexible Multi-purpose Cryptographic System on low cost FPGA

The design of cryptographic hardware that supports multiple cryptographic primitives is common in literature. In this work, a new design is presented consisting of a multi-purpose cryptographic system featuring both 128-bit pipelined AES-CORE (Advanced Encryption Standard) for high-speed symmetric encryption and a Keccak hash core on a low-cost FPGA. The KECCAK-CORE’s security and performance parameters are tunable in the sense that capacity, bitrate, and the number of rounds can be user-defined. Such flexibility enables the core to suit a large range of security requirements. The structure of Keccak’s sponge construction is exploited to enable different modes of operation. An example application outlined in this work is Pseudo Random Number Generation (PRNG). With few adjustments, the KECCAK-CORE was also operated as a post-processing unit for True Random Number Generation (TRNG) that uses the analog Lorenz chaotic circuit as a physical entropy source. The multi-purpose design was implemented in VHDL targeting an IntelFPGA Cyclone-V FPGA. For AES symmetric encryption, a maximum throughput of 31.1Gbps was achieved and a logic usage of 25146LEs (23% of the FPGA) in the case of the pipelined variant of AES-CORE. For the KECCAK-CORE, maximum throughput figures of 5.81, 8.4, and 11Gbps were achieved for the three SHA-3 variants 512, 384, and 256-bit respectively, with an area usage of 8947LEs (8%). The system as a whole occupies an area of 26909LEs (26%). The random sequences generated by the system operating in PRNG and TRNG post- processing modes successfully passed the National Institute of Standards and Technology (NIST) statistical test suite (NIST SP 800-22). The information entropy analysis performed on the post-processed TRNG sequences indicates an average of 0.935.

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multi-coarse counters and one fine counter are combined in our TDC architecture. The calibration circuit employs a START and STOP calibration signal generator and a gain calibration circuit. Arbitrarily small time intervals can be measured by distributing the START and STOP signals on different channels. In the implementation process, the high-precision external clock produced by a Silicon Si5338 EVB board and the on-chip high-precision clock are combined to calibrate the TDC output data in real-time. The TDC is implemented on a specially designed FPGA board with a low-cost Xilinx Artix-7 35T FPGA. The measured least significant bit (LSB) is 17.9 ps and the calculated peak-to-peak differential nonlinearity (DNL) and integral nonlinearity (INL) values are 1.006 and 0.920 LSB. The root-mean-square (RMS) resolution is lower than 20 ps in continuous measurement.

MCRO-PUF: A Novel Modified Crossover RO-PUF with an Ultra-Expanded CRP Space

With the expanding use of the Internet of Things (IoT) devices and the connection of humans and devices to the Internet, the need to provide security in this field is constantly growing. The conventional cryptographic solutions need the IoT device to store secret keys in its non-volatile memory (NVM) leading the system to be vulnerable to physical attacks. In addition, they are not appropriate for IoT applications due to their complex calculations. Thus, physically unclonable functions (PUFs) have been introduced to simultaneously address these issues. PUFs are lightweight and easy-to-access hardware security primitives which employ the unique characteristics of integrated circuits (ICs) to generate secret keys. Among all proposed PUFs, ring oscillator PUF (RO-PUF) has had a more suitable structure for hardware implementation because of its high reliability and easier providing of circuital symmetry. However, RO-PUF has not been so attractive for authentication purposes due to its limited supported challenge-response pairs (CRPs). A few efforts have been made in recent years that could successfully improve the RO-PUF CRP space, such as configurable RO-PUF (CRO-PUF). In this paper, by considerably improving the CRO-PUF structure and adding spare paths, we propose a novel strong RO-PUF structure that exponentially grows the CRP space and dramatically reduces the hardware cost. We implement our design on a simple and low-cost FPGA chip named XC6SLX9-2tqg144, stating that the proposed design can be used in IoT applications. In addition, to improve the CRP space, our design creates a suitable improvement in different security/performance terms of the generated responses, and dramatically outperforms the state-of-the-art. The average reliability, uniqueness, and uniformity of the responses generated are 99.55%, 48.49%, and 50.99%, respectively.

FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge

With the proliferation of low-cost sensors and the Internet of Things, the rate of producing data far exceeds the compute and storage capabilities of today’s infrastructure. Much of this data takes the form of time series, and in response, there has been increasing interest in the creation of time series archives in the past decade, along with the development and deployment of novel analysis methods to process the data. The general strategy has been to apply a plurality of similarity search mechanisms to various subsets and subsequences of time series data to identify repeated patterns and anomalies; however, the computational demands of these approaches renders them incompatible with today’s power-constrained embedded CPUs. To address this challenge, we present FA-LAMP, an FPGA-accelerated implementation of the Learned Approximate Matrix Profile (LAMP) algorithm, which predicts the correlation between streaming data sampled in real-time and a representative time series dataset used for training. FA-LAMP lends itself as a real-time solution for time series analysis problems such as classification. We present the implementation of FA-LAMP on both edge- and cloud-based prototypes. On the edge devices, FA-LAMP integrates accelerated computation as close as possible to IoT sensors, thereby eliminating the need to transmit and store data in the cloud for posterior analysis. On the cloud-based accelerators, FA-LAMP can execute multiple LAMP models on the same board, allowing simultaneous processing of incoming data from multiple data sources across a network. LAMP employs a Convolutional Neural Network (CNN) for prediction. This work investigates the challenges and limitations of deploying CNNs on FPGAs using the Xilinx Deep Learning Processor Unit (DPU) and the Vitis AI development environment. We expose several technical limitations of the DPU, while providing a mechanism to overcome them by attaching custom IP block accelerators to the architecture. We evaluate FA-LAMP using a low-cost Xilinx Ultra96-V2 FPGA as well as a cloud-based Xilinx Alveo U280 accelerator card and measure their performance against a prototypical LAMP deployment running on a Raspberry Pi 3, an Edge TPU, a GPU, a desktop CPU, and a server-class CPU. In the edge scenario, the Ultra96-V2 FPGA improved performance and energy consumption compared to the Raspberry Pi; in the cloud scenario, the server CPU and GPU outperformed the Alveo U280 accelerator card, while the desktop CPU achieved comparable performance; however, the Alveo card offered an order of magnitude lower energy consumption compared to the other four platforms. Our implementation is publicly available at https://github.com/aminiok1/lamp-alveo.

Digital Image Decoder for Efficient Hardware Implementation

Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

Design and implementation of an efficient CNN accelerator for low-cost FPGAs

Design and implementation of an efficient CNN accelerator for low-cost FPGAs

An Efficient CNN Accelerator for Low-Cost Edge Systems

Customized hardware based convolutional neural network ( CNN or ConvNet ) accelerators have attracted significant attention for applications in a low-cost, edge computing system. However, there is a lack of research that seeks to optimize at both the algorithm and hardware levels simultaneously in resource-constrained FPGA systems. In this paper, we first analyze ConvNet models to find one that is most suitable for a low-cost FPGA implementation. Based on the analysis, we select MobileNetV2 as the backbone of our research due to its hardware-friendly structure. We use a quantized implementation with 4-bit precision and optimize further with a smaller input resolution of 192 × 192 to obtain a 68.8% detection accuracy on ImageNet, which represents only a 3.2% accuracy loss compared to a floating-point model that uses the full input size. We then develop a hardware implementation that uses a low-cost FPGA. To accelerate the depth-wise separable ConvNet and utilize DRAM resources efficiently with parallel processing, we propose a novel scoreboard architecture to dynamically schedule DRAM data requests in order to maintain a high hardware utilization. The number of DSP blocks used is about six times smaller than in prior work. In addition, internal block RAM utilization is approximately nine times more efficient than in prior work. Our proposed design achieves 3.07 frames per second (FPS) on the low-cost and resource constrained FPGA system.