An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture

Abstract

This paper proposes a low-cost disparity map compression algorithm and its hardware architecture for high resolution and high frame rate applications. The proposed algorithm uses spatial correlations between neighboring disparities and has two variants. The first variant encodes the current disparity using its left neighbor, whereas the second variant benefits from left and upper neighbors. The proposed algorithm obtains 48% and 56% savings in memory space on the average for its variants. The proposed architecture can support 1080p resolution at 60 fps on a low-cost FPGA device while consuming very low area and power.