Low-cost Field Programmable Gate Array Research Articles

Efficient Pipelined Circuits for Histogram-based Tone Mapping of Nonlinear CMOS Image Sensors

Abstract Tone mapping is extensively researched to address the issue of displaying high dynamic range (DR) scenes on low DR displays. Even though several tone-mapping operators (TMOs) exist, not all are designed for hard real time. The operator has to be capable of scaling up the spatial resolution without compromising the frame rate. The implementation of a TMO should also be simple enough to embed in low-cost platforms for imaging systems. A computationally efficient, and well accepted, class of TMOs are global ones based on histograms. This work presents a method to implement TMOs that use histograms. This method is suitable for low-cost field-programmable gate arrays (FPGAs), using simple components such as adders, multipliers, and random access memories, and is particularly suited for a nonlinear CMOS image sensor (CIS) operating continuously in hard real time. The authors develop a fixed-point design, validated in bit-true fashion using Xilinx and Altera tools, from a background algorithm implemented using Matlab. Our generic design uses pipelined circuits and operates with low latency. The use of a hardware description language to model our circuits guarantees portability and modularity. Moreover, the complete TMO is generated from design parameters and a design template. The architecture is robust and scales well from kilopixel to megapixel formats. The circuits achieve 30 frames per second, at high definition resolutions, while occupying only a small fraction of the available logic elements in a low-cost FPGA device.

A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection

The echo state network (ESN) is a recently developed machine-learning paradigm whose processing capabilities rely on the dynamical behavior of recurrent neural networks. Its performance outperforms traditional recurrent neural networks in nonlinear system identification and temporal information processing applications. We design and implement a cost-efficient ESN architecture on field-programmable gate array (FPGA) that explores the full capacity of digital signal processor blocks on low-cost and low-power FPGA hardware. Specifically, our scalable ESN architecture on FPGA exploits Xilinx DSP48E1 units to cut down the need of configurable logic blocks. The proposed architecture includes a linear combination processor with negligible deployment of configurable logic blocks and a high-accuracy nonlinear function approximator. Our work is verified with the prediction task on the classical NARMA dataset and a symbol detection task for orthogonal frequency division multiplexing systems using a wireless communication testbed built on a software-defined radio platform. Experiments and performance measurement show that the new ESN architecture is capable of processing real-world data efficiently for low-cost and low-power applications.

Suppression of EMI Using Cost-Effective FPGA-Based Digital Communication Modulation Techniques in Power Converters

ABSTRACT Direct-sequence spread-spectrum (DSSS) and frequency-hopping spread-spectrum (FHSS) modulation techniques have been proposed for the operation of three-phase voltage-source rectifiers (VSR) for the mitigation of EMI in AC Grid. For the first time, in the DSSS modulation technique, binary phase shift keying and quadrature phase shift keying (QPSK) techniques have been adopted for the mitigation of electro-magnetic interference (EMI) in three-phase VSR. A cost-effective field programmable gate array (FPGA) has been employed for carrying out these proposed modulation techniques. A VHDL coding for each modulation technique is written in ISE Xilinx, verified by Model-Sim tool and then implemented using FPGA to produce gate pulses for the rectifier. Rather than building a modulator physically, the control logic is implemented using low-cost FPGA, resulting in the cost and size reduction of the control circuit. The modulation techniques recommended in this paper are compared with the traditional sinusoidal pulse width modulation (SPWM). It is shown that the FHSS and QPSK techniques proposed in this paper result in improved power quality and the conducted EMI levels are reduced by 22.1 and 12.4 dBµV, respectively, when compared with SPWM.

Digital-to-time converter for test equipment implemented using FPGA DSP blocks

This paper presents a novel digital-to-time converter (DTC) implemented using digital signal processing (DSP) blocks built in field-programmable gate array (FPGA) devices. The converter was implemented in a low-cost Xilinx Spartan-6 FPGA chip manufactured in the 45 nm CMOS process and can be applied in any other programmable logic device that contains DSP blocks. The designed DTC time interval jitter is below 2.8 ps. This is the lowest time interval jitter so far reported in such kind of circuits implemented in a programable device. The obtained resolution of up to 8.6 ps is about twice as good as that achieved in a single carry-chain-based delay-line. Furthermore, the designed circuit saves FPGA general-purpose logic (programmable logic blocks). This kind of converter can be especially useful as a part of test instrumentations as well as time-domain signal processing systems implemented in the latest generation of programmable logic devices.

Design and Implementation of a Re-Configurable Versatile Direct Digital Synthesis-Based Pulse Generator

Direct digital synthesis (DDS) technology has replaced many traditional analog circuit functions. The frequency, amplitude, and phase of a waveform generated using DDS can be precisely controlled. It is possible to achieve remarkably high-frequency resolution, fast frequency switching, and modulation can be easily introduced in a DDS generator. However, pulse waveform generated using DDS requires re-loading of the pulse waveform in the waveform memory to vary the pulse parameters, which causes phase discontinuity, requires prohibitively large memory to generate pulses with narrow widths and long periods, and suffers from trigger uncertainty of up to 1 clock period when the pulse waveform is triggered by an external event. Moreover, it is not possible to modulate the width and delay of the pulse stored in the waveform memory. This article describes a fully functional, low complexity, low cost, memory less, parallel, and DDS-based pulse waveform generator implemented in a low-cost field programmable gate arrays (FPGA) where pulse parameters such as amplitude, period, width, rise time, fall time, and delay can all be varied without any glitches or phase discontinuity, where the amplitude, frequency and phase, as well as period, width and delay of the pulse can be modulated by an internally generated or external modulating signal and where it is possible to trigger the generation of the pulse or burst of pulses by an external event where the time between the trigger event and the pulse output is fixed.

Design and Implementation of a Reconfigurable Wideband Radio Frequency Spectrum Analyzer With Image Rejection in the Digital Domain

Most existing radio frequency (RF) spectrum analyzers use conventional superheterodyne architecture to remove images associated with the down conversion of RF input frequency to some intermediate frequency (IF) for further processing, and their complexity increases as the frequency range of interest is extended. This article describes a novel digital system architecture for spectrum analyzers based on quadrature down conversion. Quadrature down conversion architectures where image responses are inherently rejected are normally used to analyze a single frequency or a very narrow frequency spectrum. This article proposes using quadrature architecture in an ultrawideband spectrum analysis application. A wideband spectrum analyzer receiver with compensation for gain and phase imbalances in the RF input range, as well as compensation for gain and phase imbalances within the IF passband complete with resolution bandwidth (RBW) filtering, video bandwidth (VBW) filtering, and amplitude detection, is implemented in a low-cost field-programmable gate arrays (FPGAs). The proposed method still achieves the desired image rejection performance specification, is power-efficient, and significantly simplifies the RF front-end hardware in comparison to state-of-the-art methods.

An easy to implement logic analyzer for long-term precise measurements

Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acquisition within small periods (less then 1 ms) during several hours or even days. The common example is real-time communication worst-case jitter analysis. This paper introduces an easy to implement approach how to create a logic analyzer for such kind of task on a basis of a low-cost Field-Programmable Gate Array (FPGA) kit and a personal computer. The Author provides both sample FPGA design files compatible with an open-source toolchain and the approach how to collect data using standard software and Octave scripts to post-process the experimental result. Following the Author’s guidelines even with minimal knowledge in FPGA design makes it easy to modify the introduced hardware for specific laboratory team needs.

DALI Bridge FPGA-Based Implementation in a Wireless Sensor Node for IoT Street Lighting Applications

Smart lighting systems based on the Digital Addressable Lighting Interface (DALI) protocol are the most suitable for street lighting systems, allowing digital lighting control operations. Unfortunately, the microcontrollers, which are commonly used in the Wireless Sensor Network nodes to control the lamps, do not implement this protocol. The DALI protocol implemented by software in the microcontroller consumes hardware resources (timers), processing time and requires a precise temporal analysis of the application, due to the strict bit times and the Manchester coding that it uses. In this work, the design of a bridge is proposed to free the microcontroller from the implementation of the DALI protocol. The novelty of this work is the implementation of the DALI Bridge in a low-cost Field-Programmable Gate Array (FPGA) with low power consumption. The bridge has been described in the hardware description language following the 1076-93 and 1076.3-97 standards, to guarantee its portability. The results of the synthesis show that a minimum amount of logical and routing resources is used, that the power consumption is in the order of tens of mW, that it has a very small latency time and that it supports a high operating frequency, which allows adding new functions. Its operation is verified by implementing a wireless sensor node using an FPGA of the Lattice Semiconductor iCE40 family.

FPGA-based neural network accelerators for millimeter-wave radio-over-fiber systems.

With rapidly developing high-speed wireless communications, the 60 GHz millimeter-wave (mm-wave) frequency range has attracted extensive interests, and radio-over-fiber (RoF) systems have been widely investigated as a promising solution to deliver mm-wave signals. Neural networks have been proposed and studied to improve the mm-wave RoF system performances at the receiver side by suppressing both linear and nonlinear impairments. However, previous studies of neural networks in mm-wave RoF systems all focus on the use of off-line processing with high-end GPUs or CPUs, which are not practical for low power-consumption, low-cost and limited computation platform applications. To solve this issue, in this paper we investigate neural network hardware accelerator implementations for mm-wave RoF systems for the first time using the field programmable gate array (FPGA), taking advantage of the low power consumption, parallel computation, and reconfigurablity features of FPGA. Both the convolutional neural network (CNN) and binary convolutional neural network (BCNN) hardware accelerators are demonstrated. In addition, to satisfy the low-latency requirement in mm-wave RoF systems and to enable the use of low-cost compact FPGA devices, a novel inner parallel computation optimization method for implementing CNN and BCNN on FPGA is proposed. It is shown that compared with the popular embedded processor (ARM Cortex A9) execution latency, the proposed FPGA-based hardware accelerator reduces the processing delay in mm-wave RoF systems by about 99.45% and 92.79% for CNN and BCNN, respectively. Compared with non-optimized FPGA implementations, results show that the proposed inner parallel computation method reduces the processing latency by about 44.93% and 45.85% for CNN and BCNN, respectively. In addition, compared with the GPU implementation, the latency of CNN implementation with the proposed optimization method is reduced by 85.49%, while the power consumption is reduced by 86.91%. Although the latency of BCNN implementation with the proposed optimization method is larger compared with the GPU implementation, the power consumption is reduced by 86.14%. The demonstrated FPGA-based neural network hardware accelerators provide a promising solution for mm-wave RoF systems.

A Novel High-Precision Synchronous Sampling Mechanism for Distributed Test System Based on Optical Fiber Network and Low-Cost Field-Programmable Gate Array

In this paper, we propose a distributed test system based on optical fiber network with multiple devices. In order to resolve the data sampling synchronicity problems, a novel synchronous sampling mechanism is developed to achieve high-precision sampling synchronicity among data acquisition devices with relatively low-cost hardware. First, we present the design of the system based on optical fiber network and the mechanism implemented in Field-Programmable Gate Array (FPGA) devices. Then, the device clocks are calibrated to run on a same frequency using a clock-disciplining algorithm for hardware implementation. In addition, propagation delays, which are used for the synchronous errors compensation during data analysis, are precisely measured using a high-precision time interval measurement approach based on delay-chain loop comparison method. A series of experiments on a real test system demonstrate the effectiveness of the proposed models and methods, and the mechanism has been employed in a general-purpose reprogrammable device cyclone-II (Altera).

A real-time FPGA accelerated stream processing for hyperspectral image classification

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

Development of a High-Performance, FPGA-Based Virtual Anemometer for Model-Based MPPT of Wind Generators

Model-based maximum power point tracking (MPPT) of wind generators (WGs) eliminates dead times and increases energy yield with respect to iterative MPPT techniques. However, it requires the measurement of wind speed. Under this premise, this paper describes the implementation of a high-performance virtual anemometer on a field programmable gate array (FPGA) platform. Said anemometer is based on a growing neural gas artificial neural network that learns and inverts the mechanical characteristics of the wind turbine, estimating wind speed. The use of this device in place of a conventional anemometer to perform model-based MPPT of WGs leads to higher reliability, reduced volume/weight, and lower cost. The device was conceived as a coprocessor with a slave serial peripheral interface (SPI) to communicate with the main microprocessor/digital signal processor (DSP), on which the control system of the WG was implemented. The best compromise between resource occupation and speed was achieved through suitable hardware optimizations. The resulting design is able to exchange data up to a 100 kHz rate; thus, it is suitable for high-performance control of WGs. The device was implemented on a low-cost FPGA, and its validation was performed using input profiles that were experimentally acquired during the operation of two different WGs.

FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

Hardware-Based Sobel Gradient Computations for Sharpness Enhancement

The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware-based imaging systems arises. These fully hardware systems solve the fundamental problem inherent in software-based solutions, in which the speed of the algorithms depend on the instruction cycle speed of the processor. Once an algorithm is designed directly on hardware, the speed of the algorithm depends on the system clock frequency and the propagation delays of the logic cells (or standard cells) used in the design, usually measured in nanoseconds per cell. Therefore, such systems no longer depend on any instruction cycle delays, as there is no microprocessor involved. Most modern imaging and communications systems rely on digital signal processing (DSP) to compute complex mathematical operations. The emergence of powerful and low-cost field-programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled the development of many such DSP hardware applications, traditionally implemented only as software solutions.

Versatile digital approach to laser frequency comb stabilization

We demonstrate the use of a flexible digital servo system for the optical stabilization of both the repetition rate and carrier-envelope offset frequency of a laser frequency comb. The servo system is based entirely on a low-cost field programmable gate array, simple electronic components, and existing open-source software. Utilizing both slow and fast feedback actuators of a commercial mode-locked laser frequency comb, we maintain cycle-slip free locking of optically-derived beatnotes over a 30 hour period and measure residual phase noise at or below ~0.1 rad, corresponding to <100 attosecond timing jitter on the optical phase locks. This stability is sufficient for high-precision frequency comb applications and indicates comparable performance to existing frequency control systems. The modularity of this system allows for it to be easily adapted to suit the servo actuators of a wide variety of laser frequency combs and continuous-wave lasers, reducing cost and complexity barriers, and enabling digital phase control in a wide range of settings.

A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement

For video applications in a special environment such as medical imaging, space exploration, and underwater exploration, the video captured by an image sensor is often deteriorated because of low lighting conditions. Therefore, it is necessary to enhance the part of the image that is too dark to distinguish details while maintaining the remaining part with the same brightness. The retinex algorithm is widely used to restore naturalness of a video, especially exhibiting outstanding performance in the enhancement of a dark area. However, it demands large computational complexity because of its intricate structure, such as the Gaussian filter and exponentiation operations, and consequently, it is difficult to process in real time. This article presents a low-cost and high-throughput design of the retinex video enhancement algorithm. The hardware (HW) design is implemented using a field-programmable gate array (FPGA), and it supports a throughput of 60 frames/s for a $1920 \times 1080$ image with negligible latency. The proposed FPGA design minimizes HW resources while maintaining the quality and the performance by using a small line buffer instead of a frame buffer, by applying the concept of approximate computing for the complex Gaussian filter, and by designing a new and nontrivial exponentiation operation. The proposed design makes it possible to significantly reduce HW resources (up to 79.22% of total resources) compared to existing systems and is compatible with commercialized devices through the standard HDMI/DVI video ports.

An Embedded System Design to Build Real-Time 2D Maps for Unknown Indoor Environments

In this paper, a remotely controllable, differentially driven wheeled mobile robot was developed in order to build 2D maps of unknown indoor environments; this system would eliminate the need to pre-explore such environments. Main aim of the study is to develop a system with high accuracy by using minimum number of sensors and a processor with low cost especially for comparatively small indoor areas. The distance traveled was calculated using the wheel odometry method. Obstacles surrounding the robot, the distance traveled, and the robot’s orientation were obtained using an ultrasonic distance sensor, optical encoder, and a 3D orientation sensor (also known as an Attitude and Heading Reference System –AHRS), respectively. In addition, the characteristics of the system hardware components were empirically explored, and the errors resulting from the sensors were evaluated. The non-linearity percentage error arising from the encoder was defined and then compensated for. The hysteresis behavior of the ultrasonic distance sensors was also empirically tested. All of the tasks were conducted by using a low-cost FPGA (Field Programmable Gate Arrays) board. This study used the graphical development platform, National Instruments (NI) LabVIEW, and it’s FPGA Module which is used for programming of embedded systems instead of the text-based HDLs (Hardware Description Languages). This distinguishes the proposed system from similar prior studies.

Low-Cost FPGA Hardware Implementation of Matrix Converter Switch Control

An idea for a hardware realization of a space vector modulation in the direct matrix converter is proposed in this brief. The method is oriented toward the implementation in a low-cost field programmable gate arrays (FPGAs). The traditional algorithms usually involve digital signal processors, which drive the large number of power transistors and “non-standard positions of control pulses” during the switching sequence. Thus, hardware implementations have become popular since particular operations are performed faster and more efficiently. This brief proposes a novel hardware algorithm for a matrix converter switch control. Contrary to the existing hardware methods, the presented technique does not require specialized modeling tools, nor advanced converters to achieve the hardware representation. Furthermore, the proposed solution permits concurrent computation of most operations. The method has been verified experimentally. The results of the hardware implementation in a low-cost FPGA are discussed.

High‐resolution FPGA‐pulse width modulation applied to PFC 2 MHz converter using eGaN field effect transistor

This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency. The PFC was implemented using a half-bridge enhancement-mode Gallium Nitride (eGaN) field effect transistor with on-board gate drives (EPC9003 development board) and the MAX10 FPGA.

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.