Low-cost Field Programmable Gate Array Research Articles

A Reliable and Cost-Effective Sand Monitoring System on the Field Programmable Gate Array (FPGA)

Sand monitoring gives the benefits of avoiding equipment erosion and production failure in the oil industry. This paper presents the design and implementation of a reliable and cost-effective sand monitoring system for measuring sand production in gas and oil flows in real time. The designed monitoring system involves two acoustic emission (AE) sensors and one Doppler sensor for gauging the sand impaction and the velocity of sand particles in a nonintrusive manner, respectively. It is implemented on a field programmable gate array (FPGA) as a prototype for real-time data acquisition and processing, and evaluated using a testbed pump skid available in our laboratory. Relying on a low-cost FPGA board to integrate all acquisition and processing functionality, our monitoring system can measure the sand production amount on-the-fly reliably with high accuracy, according to our experimental evaluation. It is likely to achieve better accuracy than one without the Doppler sensor. The proposed monitoring system is affordable for wide deployment, given its high accuracy, good resilience to surrounding noise, and low cost (when compared with commercially available systems whose price tags can be some tenfold higher).

Low-Latency Shack–Hartmann Wavefront Sensor Based on an Industrial Smart Camera

Wavefront sensing is important in various optical measurement systems, particularly in the field of adaptive optics (AO). For AO systems, the sampling rate, as well as the latency time, of the wavefront sensors (WFSs) imposes a restriction on the overall achievable temporal resolution. In this paper, we propose a versatile Shack–Hartmann WFS based on an industrial smart camera for high-performance measurements of wavefront deformations, using a low-cost field-programmable gate array as the parallel processing platform. The proposed wavefront reconstruction adds a processing latency of only 740 ns for calculating wavefront characteristics from the pixel stream of the image sensor, providing great potential for demanding AO system designs.

Solving Computationally Intensive Problems in Reconfigurable Hardware:A Case Study

In this paper we explore the effectiveness of solution of computationally intensive problems in FPGA (Field-Programmable Gate Array) on an example of Sudoku game. Three different Sudoku solvers have been implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family. The first solver is only able to deal with simple puzzles with reasoning, i.e. without search. The second solver applies breadth-first search algorithm and therefore has virtually no limitation on the type of puzzles which are solvable. We prove that despite the serial nature of implemented backtracking search algorithms, parallelism can be used efficiently. Thus, the suggested third solver explores the possibility of parallel processing of search tree branches and boosts the performance of the second solver. The trade-offs of the designed solvers are analyzed, the results are compared to software and to other known implementations, and conclusions are drawn on how to improve the suggested architectures.

All-on-Chip $dq$-Frame Based D-STATCOM Control Implementation in a Low-Cost FPGA

In power electronics equipment, digital control is essential to obtaining a proper operation of the devices. Typical implementations of this control use microprocessors, digital signal processors and Field Programmable Gate Arrays (FPGAs). In this paper, the hardware resources of an FPGA are configured in order to implement the discrete synchronism, abc/dq frame transformations, modulation, and control of a Distribution STATic COMpensator (DSTATCOM) aimed to compensate reactive current. All these tasks are implemented as independent modules to give the system the capability to reconfigure the hardware for any other application with similar requirements. Results show that FPGAs are a suitable platform to implement a power converter digital controller. Also, non-fundamental capabilities can be added to improve the controller performance, such as over-sampling, anti-windup circuits, and time multiplexing. We verify the correctness of the digital controller implemented on the FPGA device using dynamic tests on a laboratory experimental DSTATCOM low-power prototype.

Algorithmic methodologies for FPGA-based vision

This paper proposes a strategy for the design of computer vision on Field Programmable Gate Arrays (FPGAs). We show that there are certain advantages to the approach of designing an algorithm to specifically suit hardware rather than attempting to replicate the behavior of software implementations in hardware. We justify this approach through the analysis of two case studies. In the first case study, we present FPGA implementations of two corner detectors. We make a number of observations which point to the advantages of an FPGA-tailored algorithm. In the second case study, we investigate the feasibility of this approach by designing a proof-of-concept face detection algorithm that was designed specifically for an FPGA. We show that this design allows for high detection speed on a low-cost FPGA device, although the same algorithm would not be considered in software. Finally, we conclude that FPGAs offer special opportunities for specialized algorithms that are infeasible in software.

High resolution Time of Flight determination based on reconfigurable logic devices for future PET/MR systems

This contribution shows how to perform Time of Flight (TOF) measurements in PET systems using low-cost Field Programmable Gate Array (FPGA) devices with a resolution better of 100ps. This is achieved with a proper management of the FPGA internal resources and with an extremely careful device calibration process including both temperature and voltage compensation. Preliminary results are reported.

Automatic Carbon Dioxide-Methane Gas Sensor Based on the Solubility of Gases in Water

Biogas methane content is a relevant variable in anaerobic digestion processing where knowledge of process kinetics or an early indicator of digester failure is needed. The contribution of this work is the development of a novel, simple and low cost automatic carbon dioxide-methane gas sensor based on the solubility of gases in water as the precursor of a sensor for biogas quality monitoring. The device described in this work was used for determining the composition of binary mixtures, such as carbon dioxide-methane, in the range of 0–100%. The design and implementation of a digital signal processor and control system into a low-cost Field Programmable Gate Array (FPGA) platform has permitted the successful application of data acquisition, data distribution and digital data processing, making the construction of a standalone carbon dioxide-methane gas sensor possible.

Simulink Modeling and Design of an Efficient Hardware-Constrained FPGA-Based PMSM Speed Controller

The aim of this paper is to present a holistic approach to modeling and field programmable gate array (FPGA) implementation of a permanent magnet synchronous motor (PMSM) speed controller. The whole system is modeled in the Matlab Simulink environment. The controller is then translated to discrete time and remodeled using System Generator blocks, directly synthesizable into FPGA hardware. The algorithm is further refined and factorized to take into account hardware constraints, so as to fit into a low-cost FPGA, without significantly increasing the execution time. The resulting controller is then integrated together with sensor interfaces and analysis tools and implemented into an FPGA device. Experimental results validate the controller and verify the design.

Ultrasonic scanner for in vivo measurement of cancellous bone properties from backscattered data

A dedicated ultrasonic scanner for acquiring RF echoes backscattered from the trabecular bone was developed. The design of device is based on the goal of minimizing of custom electronics and computations executed solely on the main computer processor and the graphics card. The electronic encoder-digitizer module executing all of the transmission and reception functions is based on a single low-cost field programmable gate array (FPGA). The scanner is equipped with a mechanical sector-scan probe with a concave transducer with 50 mm focal length, center frequency of 1.5 MHz and 60% bandwidth at -6 dB. The example of femoral neck bone examination shows that the scanner can provide ultrasonic data from deeply located bones with the ultrasound penetrating the trabecular bone up to a depth of 20 mm. It is also shown that the RF echo data acquired with the scanner allow for the estimation of attenuation coefficient and frequency dependence of backscattering coefficient of trabecular bone. The values of the calculated parameters are in the range of corresponding in vitro data from the literature but their variation is relatively high.

Embedded Doppler system for industrial in-line rheometry

Rheological fluid behavior characterization is crucial for the industrial production of cosmetics, food, pharmaceutics, adhesive, sealants, etc. For example, the measurement of specific rheological features at every step of the production chain is critical for product quality control. Such measurements are often limited to laboratory tests on product specimens because of technical difficulties. In this work, we present an embedded system suitable for in-line rheometric evaluation of highly filled polyurethane-based adhesives. This system includes an ultrasound front-end and a digital signal processing section integrated in a low-cost field-programmable gate array. The system measures the real-time velocity profile developed in the pipe by the fluid, employing a Doppler multigate technique. The high-resolution velocity profile, combined with a pressure drop measurement, allows an accurate evaluation of the flow consistency index, K, and the flow behavior index, n, of the interrogated fluid.

Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person's identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)--SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person's identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

Codebook hardware implementation on FPGA for background subtraction

Object detection and tracking are main tasks in video surveillance systems. Extracting the background is an intensive task with high computational cost. This work proposes a hardware computing engine to perform background subtraction on low-cost field programmable gate arrays (FPGAs), focused on resource-limited environments. Our approach is based on the codebook algorithm and offers very low accuracy degradation. We have analyzed resource consumption and performance trade-offs in Spartan-3 FPGAs by Xilinx. In addition, an accuracy evaluation with standard benchmark sequences has been performed, obtaining better results than previous hardware approaches. The implementation is able to segment objects in sequences with resolution $$768\times 576$$ at 50 fps using a robust and accurate approach, and an estimated power consumption of 5.13 W.

Digital Charge Balance Controller to Improve the Loading/Unloading Transient Response of Buck Converters

A linear/nonlinear digital controller is presented that allows a Buck converter to recover from a load transient event with near-optimal voltage deviation and recovery time. A novel digital double accumulator calculation block is used to calculate the appropriate pulse width modulation switching time instants. The proposed controller possesses many advantages not demonstrated by a single controller in the previous literature. For example, unlike many previously proposed time-optimal digital controllers, the proposed controller provides an excellent transient response as it is capable of reacting asynchronously to a load transient event. In addition, it is demonstrated that the proposed controller can operate without requiring information pertaining to the Buck converter's output inductor. Furthermore, the proposed controller can be extended to applications that require load-line regulation. Lastly, unlike all previous digital time-optimal controllers, the proposed controller does not require digital multiplier or divider blocks nor does it require 2-D lookup tables. Thus, the controller can be implemented through the use of low-cost field programmable gate arrays or complex programmable logic devices.

A low-power Wave Union TDC implemented in FPGA

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Stability Analysis of FPGA-Based Control of Brushless DC Motors and Generators Using Digital PWM Technique

Brushless dc (BLDC) drives have received significant attention, owing to their high efficiency, electromagnetic interference, and high mechanical reliability due to the absence of brushes in commercial, residential, and industrial applications. In generating mode, they are very suitable for small wind and hydro generator applications, as well as integrated starter alternators in hybrid electric vehicles. This paper discusses digital pulsewidth modulation control for a BLDC drive in both motoring and generating modes of operation. This control strategy is simple and robust, requires no current sensors, and is not computationally intensive. Owing to these attributes, the technique can be implemented on a low-cost field-programmable gate array. This paper investigates potential stability issues due to the simplicity of this control under various conditions of load disturbances and also owing to the reduction in processor capability. Lyapunov stability criteria have been used to analyze the closed-loop stability of the system. Furthermore, an approximate discrete model has been developed, and the stability of the system is analyzed to ensure closed-loop operation under various sets of loads, speeds, and input voltages. Simulation and experimental results have been presented to verify the claims.

Design and implementation of a novel sliding mode sensing architecture for capacitive MEMS accelerometers

We propose novel feedback control and sensing schemes based on sliding mode control (SMC) for closed-loop micro-accelerometers as alternative digital control architectures to sigma–delta (ΣΔ) approaches. The under-damped micro-device has been designed in Coventorware, fabricated in SOIMUMPs (25 µm thick structural layer) technology and experimentally characterized using a Polytec MSA-500 (micro-system analyzer) equipment. To verify the system architecture robustness, the application of SMC is extended to an over-damped accelerometer model. In either case, the SMC demonstrates the repositioning of the proof mass to null position; however, the over-damped model exhibits shorter transition time (15 ms for 1g acceleration) due to the increased damping. In addition to that, we extend the usage of SMC beyond the classical actuation problem to a novel sensing problem where we demonstrate the extraction of the external acceleration measurement from the switching behavior along the sliding surface. An optimized fixed-point implementation is targeted on a field-programmable gate array (FPGA) using rapid prototyping methodology, where the new proposed method has been compared for reference with a control scheme that employs a ΣΔ modulator. The SMC-based architecture is advantageous in terms of hardware complexity, and the control of the number of degrees of freedom required by an inertial measurement unit can be accommodated on a low-cost FPGA device. SMC offers a sound theoretical framework for the nonlinear control of inertial sensors.

FPGA-Based Smart Sensor for Online Displacement Measurements Using a Heterodyne Interferometer

The measurement of small displacements on the nanometric scale demands metrological systems of high accuracy and precision. In this context, interferometer-based displacement measurements have become the main tools used for traceable dimensional metrology. The different industrial applications in which small displacement measurements are employed requires the use of online measurements, high speed processes, open architecture control systems, as well as good adaptability to specific process conditions. The main contribution of this work is the development of a smart sensor for large displacement measurement based on phase measurement which achieves high accuracy and resolution, designed to be used with a commercial heterodyne interferometer. The system is based on a low-cost Field Programmable Gate Array (FPGA) allowing the integration of several functions in a single portable device. This system is optimal for high speed applications where online measurement is needed and the reconfigurability feature allows the addition of different modules for error compensation, as might be required by a specific application.

FPGA-Based Vibration Analyzer for Continuous CNC Machinery Monitoring With Fused FFT-DWT Signal Processing

The industry of machine tools keeps a constant progress that responds to the most demanding market requirements, such as production-time decreasing and zero-defect manufacturing. As part of this progress, sensors and monitoring instruments have been integrated on machine tools, improving computer numerical control (CNC) and monitoring during the manufacturing process. The vibrations are one of the most significant variables to be monitored on machine tools since they directly affect the end piece finishing, tool life expectancy, general machine-tool condition, current consumption, etc. Time domain, fast Fourier transform (FFT), and discrete wavelet transform (DWT) are techniques often used for vibration analysis, because they are computationally efficient for online implementation; unfortunately, it is difficult to find an instrument for vibration analysis that allows individually applying the time, FFT, and DWT techniques, and their fusion. Moreover, the lack of instruments with characteristics such as open architecture, low cost, parallel processing, and continuous online monitoring is remarkable. The contribution of this work consists of developing a vibration-analysis instrument based on the time, FFT, DWT, and DWT-FFT fusion techniques. The instrument is implemented into a low-cost field-programmable gate array with proprietary hardware signal-processing cores in parallel for achieving real-time and continuous online analysis. Experimentation is done to show the proposed methodology efficiency and the developed-instrument versatility, focusing on industrial control applications for CNC machine tools.

A Video Elaboration System for Image Deinterlacing and Processing in Race Cars

Today, video cameras are a very common way to gather data from physical processes also thanks to the technological evolution, seen both for the acquisition devices and the visualization/elaboration ones, which brought high quality at low costs. The video world, unfortunately, still suffers from the legacies of the early analog video era, so that engineers often have to deal with artifacts whose presence is only related to the will of remaining compatible with such old video technologies, among which the interlacement is certainly one of the most problematic ones. In this letter, we will present a work, in collaboration with the Magneti Marelli Motorsport division, aimed at developing a video acquisition system to be installed on F1 race cars for tire or wing monitoring, together with a low-cost field-programmable gate array (FPGA)-based video deinterlacer, which would allow them to use analog cameras whenever they are unable to use a digital one.