Low-cost Field Programmable Gate Array Research Articles

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

ADC-Based Embedded Real-Time Simulator of a Power Converter Implemented in a Low-Cost FPGA: Application to a Fault-Tolerant Control of a Grid-Connected Voltage-Source Rectifier

This paper deals with embedded real-time (RT) simulators applied in power electronic applications and implemented in low-cost field-programmable gate arrays. Indeed, such simulators' intellectual properties (IPs) are not only intended for hardware-in-the-loop (HIL) testing but also can be advantageously embedded within digital controllers to ensure functions such as observation, estimation, diagnostic, or health monitoring. Conversely, to the HIL case, the main challenge when designing such simulators' IPs is to cope with their complexity having in mind that, in the case of embedded systems, the available hardware resources are limited due to the cost. Furthermore, this challenge is strengthened by the need of very short simulation time steps that is typically the case when simulating power converters. By this way, this paper presents the design of an embedded RT simulator of a three-phase grid-connected voltage-source rectifier, based on the associated discrete circuit modeling approach. This IP is associated with the one of a three-phase $RL$ filter, and both are implemented within the rectifier controller to estimate the grid currents. The latter is injected in the controller when a fault is detected in the current sensors. The ability of this estimator to guarantee the service continuity in case of faults has been validated through HIL tests and experiments.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter (DPD). The architecture is implemented on field programmable gate array (FPGA) to compensate for the nonlinearity of the concurrent dual-band power amplifier (PA). This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables (LUTs) sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio (ACPR) is less than 59 dBc and normalized mean square error (NMSE) is around 62dB for lower sideband (LSB) and 63dB for upper sideband (USB).

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.

A single chip FPGA-based solution for controlling of multi-unit PMSM motor with time-division multiplexing scheme

The use of multiple unit controllers for parallel processing of multi-unit motor drive systems can significantly reduce the execution time of the control algorithm. However, this approach does not only increase the system cost but also incurs in additional cost of hardware and software interconnections. This paper presents a fully integrated single chip field programmable gate array (FPGA) based solution for controlling of an independent multi-unit permanent magnet synchronous motor (PMSM) drive system with space vector pulse width modulation (SVPWM) based vector control. For multi-unit motor systems, the complexity of control algorithms often exceeds the resource availability of low-cost FPGA devices. Thus, a system-level time-division multiplexing scheme applicable for multi-motor control systems is proposed. Using the proposed method, large identical complex control algorithms can be simplified into a single compact algorithm, which is fitted and configured into a low-cost FPGA. Simulation modeling and experimental results are shown, confirming the effectiveness of a multi-unit PMSM motor drive system using an inexpensive controller based on system-level time-division multiplexing scheme, which can operate simultaneously with robustness under different operating conditions.

Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

Low‐cost and high‐speed hardware implementation of contrast‐preserving image dynamic range compression for full‐HD video enhancement

This study presents a cost-efficient and high-performance field programmable gate array (FPGA)-based hardware implementation of a contrast-preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware-friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed-point unsigned binary addition, multiplication, and bit-shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on-chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high-definition videos (1920 × 1080 pixels) at least 80 frames per second using a low-cost FPGA device.

Giant-Magnetoresistance-Based Galvanically Isolated Voltage and Current Measurements

Nowadays, dc current is much more widely used than a decade ago, not only in the well-known high-voltage dc transmission but also as dc-powered marine systems, dc data centers, and dc fast charging systems for electric vehicles. However, galvanically isolated dc voltage or current sensors are, in terms of accuracy, noise level, or dimensions, still far behind the ac measurement devices in low and medium voltage areas. In this paper, a giant-magnetoresistive-based sensor system for galvanic isolated dc current and voltage measurements is introduced. The system mainly consists of a special coil arrangement with low inductance for voltage measurement, a special U-turn for current measurement, and A/D converters with a low-cost field-programmable gate array for signal conditioning. The sensor system showed an outstanding measurement accuracy of 0.3% for voltage values up to ±550 V and 0.2% for current values up to ±100 A in a temperature range from −30 °C to 90 °C. This completely new approach for the galvanically isolated measurement of electric voltage and current avoids the use of bulky magnetic components and expensive power-consuming analog electronics, which allows one to integrate it in the current ac measure unit for power monitoring.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

An Efficiency Multiplexing Scheme and Improved Sampling Method for Multichannel Data Acquisition System

The paper proposes an efficient multiplexing scheme that is easy to realize synchronous sampling in a multichannel acquisition system with the large number of analogue inputs and different sampling rates. And then, a simple improved sampling control method is also employed to improve the performance. All the technology of implementing the method is by using a low-cost field programmable gate array (FPGA). A sampling lookup table is built by the rule-based synchronous sampling frame structure for the input analogue multiplexers and stored into the internal block RAM resource in the FPGA to reduce the internal wiring resources and optimize the utilization. The improved sampling method obtains several samples in a sampling period and gets the average value as the final output for the sampling channel. In addition, the standard sine wave FFT test method is implemented to test the dynamic parameters of the acquisition channels. The experiment results show that the dynamic performance of the acquisition system is significantly improved. The proposed multiplexing scheme and sampling method can easily be reconfigured for other applications.

A Low-cost Reconfigurable Field-programmable Gate Array Based Three-phase Shunt Active Power Filter for Current Harmonic Elimination and Power Factor Constraints

Non-linear loads, such as switched mode power supply, adjustable-speed drives, arc furnaces, etc., result in deterioration of power quality in terms of current harmonics and reactive power demand. Shunt active power filters are widely used to compensate the current harmonics, thereby improving power quality. Digital signal processors and microcontroller units used in digital control of shunt active power filters are constrained by a complex algorithm structure, adaptability, accuracy, the absence of feedback loop delays, and larger execution time. Shunt active power filters require a faster computation update rate to maintain the closed-loop bandwidth, accurate sensing of voltage and current, proper estimation of parameters, and a high frequency pulse-width modulation. In this article, a low-cost single all-on-chip field-programmable gate array implements the digital control of a three-phase shunt active power filter. This proposed implementation scheme has much less execution time and boosts the overall performance of the system. All required tasks of a typical shunt active power filter are implemented with a low-cost single all-on chip field-programmable gate array module that provides freedom to reconfigure for any other applications. Additional features, such as anti-windup, over-sampling, and time multiplexing, are also added to improve the overall performance. The proposed system is designed to meet IEEE 519 and IEC EN 61000-3 recommendations in terms of harmonic elimination and unity power factor requirements. The entire algorithm is coded, processed, and simulated using Xilinx 12.1 ISE Suite to estimate the advantages of the proposed system. This code is also defused on the low-cost single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype, and experimental results obtained match with simulated counterparts. The proposed control scheme for the shunt active power filter results in reduces current harmonics under dynamic and steady-state operating conditions.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3ps and the measurement standard deviation is about 61.7ps within the measurement range of 5ns.

Field‐programmable gate array‐based linear–non‐linear control with high‐resolution digital pulse width modulator and high‐speed embedded analogue‐to‐digital converter for multi‐phase voltage regulator modules

Power converters for applications with high switching frequency and tight output voltage regulation such as voltage regulator modules (VRM) for microprocessors power supplies require fast dynamic response to meet the specifications. An existing control technique known as linear-non-linear (LnL) control strategy allows improving the transient converter response by means of an easy rule for the saturation of the duty cycle. The use of a digital implementation can optimise the transient response of the multi-phase VRM with LnL. However, digital control leads to other problems derived from time discretisation and finite word length effects. The limited resolution and the sampling delay are critical issues for digital control implementation of multi-phase VRM with LnL control. As a result, a high-resolution digital pulse width modulator (DPWM) and high-speed analogue-to-digital (A/D) converter are required to obtain proper performance of the converter. This study is focused on the digital implementation of the well-known LnL control in a multi-phase VRM taking advantage of low-cost field-programmable gate array resources. A detailed description of the digital implementation of the main converter control blocks, which are the A/D converter, the compensator and the DPWM, is provided in the paper.

Design of Low Cost Sigma-Delta Analog-to- Digital Converter for Audio Applications

FPGA (Field-Programmable Gate Array) based solutions in consumer electronics have gained popularity due to low cost and high performance. The time-to market is also shorter and the financial risk is lower compared to ASIC (Application Specific Integrated Circuit). One component that is missing in a low-cost FPGA is the ability to convert an analog signal to its digital counterpart. The aim of this paper is to implement an ADC (Analog-to- Digital Converter) for audio applications using external components together with an FPGA (Field- Programmable Gate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bit resolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually some unused pins and logic available in the FPGA that can be used for other purposes. This is taken advantage of, to make the ADC as low-cost as possible. This paper presents two types of converters an Σ- ∆ (Sigma-Delta) converter with a first order passive loop-filter and an Σ-∆ converter with a second order active loop-filter. The solutions have been designed on a PCB (Printed Circuit Board) with a Xilinx Spartan FPGA. Both solutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers in the FPGA. First converter achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effective number of bits10.06 bits)and it is very low-cost but is not suitable for high-precision audio applications. Second converter achieves a peak SNDR of 80.3 dB (ENOB 13.04) and the cost is more comparatively first one but it is more suitable for mono audio and for stereo audio applications.

High-Speed Simultaneous Image Distortion Correction Transformations for a Multicamera Cylindrical Panorama Real-time Video System Using FPGA

This paper presents a field-programmable gate array (FPGA) real-time multicamera cylindrical panorama video system. In this system, a novel simultaneous image transformation method has been studied (Chinese pattern pending No. 201310059020.1). Based on this method, perspective transformation, barrel correction, and cylindrical projection have been done at the same time for a multicamera system, resulting in an improvement of the overall performance. Using a low-cost parallel FPGA architecture, a high-speed real-time panoramic video system with low latency and high-performance has been developed. This video system can generate panoramic video of 5 \(\times \) 1280(H) \(\times \) 720(V)@15 frames/s or 5 \(\times \) 1280(H) \(\times \) 360(V)@30 frames/s in real-time on Xilinx Spartan6-150T FPGA. In order to display the panoramic video, a hardware display structure that can output the panoramic video in slide mode has also been constructed.

Low cost FPGA based data acquisition system for a gamma imaging probe

We present the development of a low cost field programmable gatearrays (FPGA) based data acquisitionsystem for a gamma imaging probe proposed for sentinel lymph node (SLN) mapping.Radioguided surgery using a gamma probe is an established practice and has beenwidely introduced in SLN biopsies. For such applications, imaging systemsrequirecompact readout electronics and flexibility. Embedded systems implemented in theFPGA technology offer new possibilities indata acquisition for nuclear medicine imagers. FPGAs are inexpensive compared toapplication specific integrated circuits (ASICs), usually used for the readoutelectronics of dedicated gamma cameras and their size is rather small.In this study, cost effective analog to digital converters (ADCs) were used andsignalprocessing algorithms were implemented in the FPGA to extract the energy andposition information. The analog front-end electronics were carefully designedtakinginto account the low sampling rate of the ADCs. The reference gamma probe has asmall fieldof view (2.5 cm × 2.5 cm) and is based on the R8900U-00-C12 positionsensitive photomultiplier tube (PSPMT) coupled to a pixellated CsI(Na)scintillator with 1 mm × 1 mm × 5 mm crystal element size. Measurementswere carried out using a general purpose collimatorand 99mTc sources emitted at 140 keV. Performance parameters for theimaging gamma probe werecompared with those obtained when data were acquired using the standard NIM(NuclearInstrumentation Modules) electronics and found to be in very good agreement,which demonstrates the efficiency of the proposed implementation.

Simple Digital Pulse Width Modulator Under 100 ps Resolution Using General-Purpose FPGAs

This letter describes a very simple implementation of a digital pulse width modulator (DPWM) under 100 ps resolution in low-cost field-programmable gate arrays (FPGAs). The implementation is based on internal carry chains and logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources, and does not rely heavily on specialized phase-locked loop or clock management resources. A 50-MHz switching frequency DPWM with 60-ps resolution and a 1-MHz switching frequency DPWM with 90-ps resolution are experimentally demonstrated, with monotonicity and excellent linearity.

Design and Implementation of an Interpolation Processor for CNC Machining

As the demand for high speed and high precision machining increases, the fast and accurate real-time interpolation is necessary in modern computerized numerical control (CNC) systems. However, the complexity of the interpolation algorithm is an obstacle for the embedded processor to achieve high performance control. In this paper, a novel interpolation processor is designed to accelerate the real-time interpolation algorithm. The processor features an advanced parallel architecture, including a 3-stage instruction pipeline, very long instruction word (VLIW) support, and asynchronous instruction execution mechanism. The architecture is aimed for accelerating the computing-intensive tasks in CNC systems. A prototype platform was built using a low-cost field programmable gate array (FPGA) chip to implementation the processor. Experimental result has verified the design and showed the good computing performance of the proposed architecture.

A Systematic Approach for Implementing Fractional-Order Operators and Systems

In this paper a generalized class of fractional-order systems is realized in digital hardware using a low-cost field programmable gate array (FPGA) device. First, fractional-order derivatives and integrals are realized in fixed-point hardware, wherein each coefficient and signal is represented with a custom number of bits. Both shift-form and delta-form structures are used for discretization, and are combined in the digital hardware realization to achieve a desired accuracy with low hardware cost. A methodology is then developed to construct general fractional-order transfer functions using the fractional-order derivatives and integrals as building blocks, in the same way that their integer-order counterparts are used in an integer-order system. Three systems are presented to illustrate the methodology using partitioned-form and feedback-form realization structures; the hardware results verify that the high-speed realizations achieve the desired accuracy with a low-cost solution.

A time digitizer for space instrumentation using a field programmable gate array

Space instruments such as time-of-flight (TOF) mass spectrometers and altimeters rely on time-to-digital converters (TDCs) to measure accurately times in the picosecond to microsecond range. Time-to-digital conversion is often implemented with analog circuitry or more recently with custom ASIC (Application Specific Integrated Circuit) devices. The analog approach may be costly in terms of circuit board area and parts count, while ASIC development is risky and costly when system requirements may change. Here, we present a highly flexible, accurate, and low-cost field-programmable gate array (FPGA) implementation of such TDC functionality. Compared with other technologies, this method reduces the parts count in TOF-supporting circuits and provides design flexibility in TOF instrumentation, especially for use in space or for applications with a number of sensors too small to warrant the development of a dedicated ASIC. Our technique can accommodate one or more STOP pulse measurements for each START pulse as signal reference, effectively providing measurements of multiple times-of-flight with the same start trigger. Alternatively, all pulse event edges can receive an absolute time stamp, enabling a broad set of new sensor applications. This novel design is based on the construction of a delay-line internal to the FPGA. Propagation variations due to temperature and supply voltage, which typically limit FPGA-based timing designs, are automatically compensated, allowing active signal processing 100% of the time. A methodology for the characterization of internal delay-line timing and nonlinearity has also been developed and is not specific to a particular FPGA architecture. We describe the design of this FPGA-based TDC and also describe detailed tests with a Xilinx XC2V1000. For single non-repetitive events, this design achieves 60 ps accuracy (standard deviation of error); a simplified implementation is suitable for non-reprogrammable FPGAs.